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參數(shù)資料
| 型號： | LC662106A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM |
| 中文描述： | 四位單片機與4,6微控制器和8 KB的片上ROM |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 104K |
| 代理商： | LC662106A |
No. 5996-11/13
LC662104A, 662106A, 662108A
Parameter
Symbol
Conditions
Ratings
typ
min
max
Unit
Note
P2, P3 (except for the P33/HOLD pin), P4,
P51, and P53: V
IN
= 13.5 V, with the output
Nch transistor off
I
IH
1
5.0
μA
1
Input high-level current
I
IH
2
P0, P1, P50, P52, OSC1, RES, and P33/HOLD:
V
IN
= V
DD
, with the output Nch transistor off
P0, P1, P2, P3, P4, and P5:
V
IN
= V
SS
, with the output Nch transistor off
P2, P3 (except for the
1.0
μA
1
Input low-level current
I
IL
1
–1.0
μA
2
Output high-level voltage
V
OH
1
I
OH
= –1 mA
I
OH
= –0.1 mA
V
DD
– 1.0
V
DD
– 0.5
V
3
P33/HOLD pin)
Value of the output pull-up resistor
R
PO
P0, P1, P4, P5
30
100
150
k
V
OL
1
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): I
OL
= 1.6 mA
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): I
OL
= 8 mA
P2, P3, P4, P51, and P53: V
IN
= 13.5 V
Does not apply to P2, P3, P4, P51, and P53:
V
IN
= V
DD
0.4
V
5
Output low-level voltage
V
OL
2
1.5
V
I
OFF
1
5.0
μA
6
Output off leakage current
I
OFF
2
1.0
μA
6
[Schmitt characteristics]
Hysteresis voltage
V
HYS
Vt
H
Vt
L
0.1 V
DD
High-level threshold voltage
P2, P3, P4, P5, and RES
0.5 V
DD
0.2 V
DD
0.8 V
DD
0.5 V
DD
V
Low-level threshold voltage
V
[Ceramic oscillator]
Oscillator frequency
f
CF
f
CFS
OSC1, OSC2: See Figure 2. 4 MHz
4.0
MHz
Oscillator stabilization time
See Figure 3. 4 MHz
10.0
ms
[Serial clock]
Cycle time
Input
t
CKCY
0.9
μs
Output
2.0
Tcyc
Low-level and high-level Input
pulse widths
t
CKL
t
CKH
0.4
μs
Output
1.0
Tcyc
Rise an fall times
Output
t
CKR
, t
CKF
0.1
μs
[Serial input]
Data setup time
t
ICK
0.3
μs
Data hold time
t
CKI
0.3
μs
[Serial output]
SO0: With the timing of Figure 4 and the test
load of Figure 5. Stipulated with respect to the
falling edge (
↓
) of SCK0.
Output delay time
t
CKO
0.3
μs
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
t
IOH
, t
IOL
2
Tcyc
High and low-level pulse widths
for interrupt inputs other than INT0
t
IIH
, t
IIL
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
2
Tcyc
RES high and low-level
pulse widths
t
RSH
, t
RSL
RES: Figure 6, conditions under which reset
can be applied.
3
Tcyc
Operating current drain
I
DD OP
V
DD
: 4-MHz ceramic oscillator
V
DD
: 4-MHz external clock
V
DD
: 4-MHz ceramic oscillator
V
DD
: 4-MHz external clock
V
DD
: V
DD
= 1.8 to 5.5 V
4.5
8.0
mA
8
4.5
8.0
mA
Halt mode current drain
I
DDHALT
2.5
5.5
mA
2.5
5.5
mA
Hold mode current drain
I
DDHOLD
0.01
10
μA
SI0: With the timing of Figure 4.
Stipulated with respect to the rising edge (
↑
) of
SCK0.
SCK0: With the timing of Figure 4 and the test
load of Figure 5.
Electrical Characteristics
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 3.0 to 5.5 V unless otherwise specified.
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
6. With the output Pch transistor off for open-drain output specification pins.
7. Reset state
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| LC662108A | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM |
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