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參數(shù)資料
| 型號(hào)： | LC65P1104 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Chip UVEPROM 4-Bit Single-Chip Microcontroller |
| 中文描述： | 片上UVEPROM 4位單片機(jī) |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 265K |
| 代理商： | LC65P1104 |
No. 5221-16/19
LC65E1104
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
I
IH
1
Port C, D, E, F: Output Nch Tr. OFF, (Including the Nch.
transistor off state leakage current.), V
IN
= +13.5
Port A, G: Output Nch Tr. OFF, (Including the Nch.
transistor off state leakage current.), V
IN
= V
DD
OSC1: External clock mode, V
IN
= V
DD
Port of OD type: Output Nch Tr. OFF, V
IN
= V
SS
RES: V
IN
= V
SS
OSC1: External clock mode, V
IN
= V
SS
Port: I
OL
= 10 mA
Port: I
OL
= 1 mA, I
OL
of each port; 1 mA or less
+5.0
μA
High-level input current
I
IH
2
+5.0
μA
I
IH
3
I
IL
1
I
IL
2
I
IL
3
V
OL
1
V
OL
2
+1.0
μA
–1.0
μA
Low-level input current
–150
–50
μA
–1.0
μA
Low-level output voltage
1.5
V
0.5
V
[Schmitt characteristics]
Hysteresis voltage
VHIS
0.1 V
DD
V
High-level threshold voltage
VtH
RES, INT, SCK, SI, OSC1 of Schmitt type
*
4
0.4 V
DD
0.25 V
DD
0.8 V
DD
0.6 V
DD
V
Low-level threshold voltage
VtL
V
[Current drain]
Ceramic resonator oscillator
IDDOP1
5
8
mA
External clock
IDDOP2
5
8
Standby mode
IDDst
V
DD
: Output Nch Tr. OFF, V
DD
= 6 V
V
DD
: Port = V
DD
, V
DD
= 3 V
0.05
10
μA
0.025
5
μA
[Oscillator characteristics]
Ceramic resonator oscillator
fCFOSC
OSC1, OSC2: Fig.2, fo = 4 MHz
*
5
3840
4000
4160
kHz
Frequency stabilization time
tCFS
Fig. 3, fo = 4 MHz
10
ms
[Pull-up resistance]
I/O port RES
RU
RES: V
IN
= V
SS
, V
DD
= 5 V
50
100
250
k
[External reset characteristics]
Reset time
tRST
See Fig. 4
Pin capacitance
C
P
f = 1 MHz. V
IN
= V
SS
for all pins other than those
being tested.
10
pF
[Serial clock]
Input clock cycle time
tCKCY1
SCK: Fig. 5
2.0
μs
Output clock cycle time
tCKCY2
SCK: Fig. 5
64
×
tCYC
*
6
μs
Input clock low-level pulse width
tCKL1
SCK: Fig. 5
0.6
μs
Output clock low-level pulse width
tCKL2
SCK: Fig. 5
32
×
tCYC
μs
Input clock high-level pulse width
tCKH1
SCK: Fig. 5
0.6
μs
Output clock high-level pulse width
tCKH2
SCK: Fig. 5
32
×
tCYC
μs
[Serial input]
Data setup time
tICK
SI: Specified from the rising edge of SCK. Fig. 5
0.2
μs
Data hold time
tCKI
0.2
μs
[Serial output]
Output delay time
tCKO
SO: Specified from the falling edge of SCK. Nch OD
only, external 1 k
, external 50 pF, Fig.5
0.4
μs
[Pulse output]
Period
tPCY
64
×
tCYC
32
×
tCYC
± 10%
32
×
tCYC
± 10%
μs
High-level pulse width
tPH
μs
Low-level pulse width
tPL
μs
PE0: Fig. 6, tCYC = 4
×
system clock period,
Nch OD only, external 1 k
, external 50 pF
V
DD
: Fig. 2, 4 MHz, 200 kHz to 4330 kHz
*
Note:
*
Output Nch Tr. OFF at operating mode,
port = V
DD
Electrical Characteristics
at Ta = +10 to +40°C, V
SS
= 0 V, V
DD
= 4.0 to 6.0 V
Continued on next page.
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