參數(shù)資料
型號(hào): LC6527F
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-chip 4-bit Microcomputer for Small-scale Control-oriented Applications(用于小規(guī)??刂贫ㄎ粦?yīng)用的單片4位微控制器)
中文描述: 單芯片四小規(guī)模的控制位微機(jī)化應(yīng)用(用于小規(guī)??刂贫ㄎ粦?yīng)用的單片4位微控制器)
文件頁數(shù): 30/43頁
文件大?。?/td> 1469K
代理商: LC6527F
LC6527N/F/L, LC6528N/F/L
No. 4363-30/43
LC6527, 6528 Instruction Set (by function)
Symbol
AC
ACt
CF
DP
E
M
M (DP)
Description
: Accumulator
: Accumulator bit t
: Carry flag
: Data pointer
: E register
: Memory
: Memory addressed
by DP
Mnemonic
Instruction code
Function
Description
Status flag
affected
Remarks
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CLA
Clear AC
1 1 0 0
0 0 0 0
1 1 AC
0
ZF
*1
CLC
Clear CF
1 1 1 0
0 0 0 1
1 1 CF
0
CF
STC
Set CF
1 1 1 1
0 0 0 1
1 1 CF
1
CF
CMA
Complement AC
1 1 1 0
1 0 1 1
1 1 AC
(AC)
ZF
INC
Increment AC
0 0 0 0
1 1 1 0
1 1 AC
(AC) + 1
ZF CF
DEC
Decrement AC
0 0 0 0
1 1 1 1
1 1 AC
(AC) – 1
ZF CF
TAE
Transfer AC to E
0 0 0 0
0 0 1 1
1 1 E
(AC)
XAE
Exchange AC with E
0 0 0 0
1 1 0 1
1 1 (AC)
(E)
INM
Increment M
0 0 1 0
1 1 1 0
1 1 M(DP)
[M (DP)] + 1
ZF CF
DEM
Decrement M
0 0 1 0
1 1 1 1
1 1 M(DP)
[M(DP)] – 1
ZF CF
SMB bit
Set M data bit
0 0 0 0
1 0 B
1
B
0
1 1 M(DP, B
1
B
0
)
1
RMB bit
Reset M data bit
0 0 1 0
1 0 B
1
B
0
1 1 M(DP, B
1
B
0
)
0
ZF
AD
Add M to AC
0 1 1 0
0 0 0 0
1 1 AC
= (AC) + [M(DP)]
ZF CF
ADC
Add M to AC with CF
0 0 1 0
0 0 0 0
1 1 AC
(AC) + [M(DP)]
+(CF)
ZF CF
DAA
Decimal adjust AC in
addition
1 1 1 0
0 1 1 0
1 1 AC
(AC) + 6
ZF
DAS
Decimal adjust AC in
subtraction
1 1 1 0
1 0 1 0
1 1 AC
(AC) + 10
ZF
EXL
Exclusive or M to AC
1 1 1 1
0 1 0 1
1 1 AC
(AC) Y [M(DP)]
ZF
CM
Compare AC with M
1 1 1 1
1 0 1 1
1 1 [M(DP)] + (AC) + 1
ZF CF
P(DP
L
)
: Input/output port
addressed by DP
L
: Program counter
: Stack register
: Timer
: Timer (internal)
interrupt request flag
: Zero flag
PC
STACK
TM
TMF
ZF
( ), [ ]
+
Y
: Contents
: Transfer and direction
: Addition
: Subtraction
: Exclusive OR
B
C
The AC contents are cleared.
The CF contents are cleared.
The CF is set.
The AC contents are
complemented.
The AC contents are
incremented +1.
The AC contents are
decremented –1.
The AC contents are
transferred to the E.
The AC contents and the E
contents are exchanged.
The M(DP) contents are
incremented +1.
The M(DP) contents are
decremented –1.
A single bit of the M(DP)
specified with B
1
B
0
is set.
A single bit of the M(DP)
specified with B
1
B
0
is reset.
Binary addition of the AC
contents and the M(DP)
contents is performed and the
result is stored in the AC.
Binary addition of the AC, CF
contents and the M(DP)
contents is performed and the
result is stored in the AC.
6 is added to the AC contents.
10 is added to the AC contents.
The AC contents and the
M(DP) contents are exclusive
OR ad and the result is stored
in the AC.
The AC contents and the
M(DP) contents are compared
and the CF and ZF are set/
reset.
Comparison result CF
ZF
[M(DP)] > (AC)
0
0
[M(DP)] = (AC)
1
1
[M(DP)] < (AC)
1
0
I
g
A
M
i
A
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