參數(shù)資料
型號(hào)： LC5768VG-10F484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 9/99頁
文件大?。?/td> 0K
描述： IC XPLD 768MC 10NS 484FPBGA
標(biāo)準(zhǔn)包裝： 60
系列： ispMACH™ 5000VG
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 24
宏單元數(shù)： 768
輸入/輸出數(shù)： 304
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
13
FIFO Mode
In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The
read and write clocks can be different or the same dependent on the application. Four flags show the status of the
FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro-
grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica-
tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read
address.
In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 12 shows the block diagram of the FIFO.
Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share
the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead
mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared
by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg-
isters.
Figure 12. FIFO Block Diagram
Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode
Register
Input
Source
Write Data,
Write Enable
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
N/A
Full and
Almost Full
Flags
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
Read Data,
Empty and
Almost Empty
Flags
Clock
RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
‘
68 Inputs
From
Routing
Write Clock (WCLK)
Write Enable (WE)
Reset (RST)
Read Enable (RE)
Read Clock (RCLK)
Reset_RP (RSTRP)
Write Data
(DI[0:0-31])
16,384-bit
SRAM
Array
FIFO
Control
Logic
*Control logic can be
duplicated in adjacent MFB
in 32-bit mode
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(DO[0:0-31])
FIFO
Flags*
Full, Empty,
Almost Full,
AlmostEmpty
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
MIC5252-2.85BML TR IC REG LDO 2.85V .15A 6-MLF
M5LV-512/120-15YI IC CPLD 512MC 120I/O 160PQFP
REC3-483.3SRW/H/B CONV DC/DC 3W 36-72VIN 3.3VOUT
EEC06DRYN-S13 CONN EDGECARD 12POS .100 EXTEND
GEC31DTEI CONN EDGECARD 62POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5768VG-12F256I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5768VG-12F484I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5768VG-5F256C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5768VG-5F484C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5768VG-5FN484C 制造商:Lattice Semiconductor Corporation 功能描述:CPLD ispMACH 5000VG Family 768 Macro Cells 178.6MHz 3.3V 484-Pin FBGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*