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參數(shù)資料
| 型號： | LC4132C |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | LC4132C |
No. 6477-6/12
LC4132C
Pin Functions
Pin
I/O
Function
LCD drive outputs
O1 to O240
O
V0 level drive voltage application (selected level)
V2 level drive voltage application (unselected level)
V3 level drive voltage application (unselected level)
V5 level drive voltage application (selected level)
V0
V2
V3
V5
I
I
I
I
M
Data
DISP
On
H
H
H
V0
H
L
H
V2
L
L
H
V3
L
H
H
V5
*
*
L
V5
R/L
EIO1
EIO2
L
IN
OUT
H
OUT
IN
R/L
BS
O1 to O240 outputs
→
↑
D4
→
↑
D3
→
↑
D0
→
↑
D3
O1
↑
D7
O2
↑
D6
O3
↑
D5
O4
...
O237 O238 O239 O240
↑
↑
D3
D2
L
↑
↑
H
D1
D0
O1
↑
D0
O2
↑
D1
O3
↑
D2
O4
...
O237 O238 O239 O240
↑
↑
D4
D5
H
↑
↑
D6
D7
O1
↑
D3
O2
↑
D2
O3
↑
D1
O4
...
O237 O238 O239 O240
↑
↑
D3
D2
L
↑
↑
L
D1
D0
O1
↑
D0
O2
↑
D1
O3
↑
D2
O4
...
O237 O238 O239 O240
↑
↑
D0
D1
H
↑
↑
D2
D3
High-voltage system power supply
V
DDH
—
Logic system power supply
V
DD
—
GND
V
SS
—
LCD off function. When this pin is low, all outputs are held at the V5 level.
DISP
I
Alternation signal input
M
I
Enable I/O
Enable input: The enable input at the initial stage is fixed at the V
SS
level, and the enable inputs of later stages are connected to
the enable output from the previous stage.
Enable output: When cascade connection is used, the enable output is connected to the enable input of the next stage.
EIO1
EIO2
I/O
I/O
Data acquisition clock (falling edge)
CP
I
Data load clock (falling edge)
LOAD
I
Data shift direction setting
R/L
I
Parallel data inputs
D0 to D7
I
Input bus width setting. A high level selects 8-bit input, and a low level selects 4-bit input. In 4-bit input mode, D0 to D3 are used
for data acquisition and D4 to D7 must be tied to ground.
BS
I
*
don't care
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