- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358751 > LC11014-241 (Sanyo Electric Co.,Ltd.) Computer Image Signal Processing Full-Color Gray-Scale Processor PDF資料下載
參數(shù)資料
| 型號： | LC11014-241 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Computer Image Signal Processing Full-Color Gray-Scale Processor |
| 中文描述： | 計算機圖像信號處理全彩色灰度處理器 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大小： | 534K |
| 代理商： | LC11014-241 |
LC11014-241
No. 5578—5/13
SRD0 [7:0]
86 to 89, 92 to 95
I
Input pins for red, green and blue gray-scale data. SRD07, SRD17, SGD07, SGD17, SBD07, SBD17 are
the MSBs. SRD00, SRD10, SGD00, SGD10, SBD00, SBD10 are the LSBs. Input data 00
to minimum brightness, and FF
H
occur when an input is set to either the minimum or maximum. If 2-pixel data is set on both S
S
×
D1, the display data on S
×
D0 is displayed first. In input/output modes 1 and 2, inputs SRD1[0:7],
SGD1[0:7] and SBD1[0:7] should be tied high or low.
H
corresponds
to maximum brightness. Note that correct gray-scale display does not
×
D0 and
SRD1 [7:0]
96 to 99, 101 to 104
I
SGD0 [7:0]
105 to 107,
110 to 114
I
SGD1 [7:0]
115 to 117,
119 to 123
I
SBD0 [7:0]
124, 125, 128 to 133
I
SBD1 [7:0]
134, 136 to 142
I
SHSYNC
79
I
Horizontal and vertical synchronization signal inputs. These are the sources for the HSYNC and VSYNC
signals. They are also used to control data processing. Active-low signals.
SVSYNC
80
I
SHDEN
78
I
Horizontal data valid-period signal input. Set this pin high during periods when the horizontal data is
valid. If this signal is not used, tie it high and set the input data to 0 during the horizontal blanking period.
SCTL
83
I
LCD control signal input. Input control signal that must be matched to the data signal timing. This is the
source for the CTL signal. If the CTL signal is not used, there is no internal signal processing of this input
and hence there is no need to input the SCTL signal.
CLKSEL
8
I
CLKSEL is the dot clock output select pin. It is used to select the output mode of the dot clock signal
output pin.
In input/output modes 0 and 2: When CLKSEL is low, a signal with the opposite phase from SCLK is
output from CLK. When CLKSEL is high, a signal with the same phase as SCLK is output from CLKB.
In input/output mode 1: When CLKSEL is low, a signal with half the frequency of SCLK is output from
CLK. When CLKSEL is high, a signal with the opposite phase from CLK is output from CLKB.
CLK
66
O
CLKB
69
O
RD0 [0:5]
52 to 53, 56 to 59
O
Red, green and blue gray-scale data output pins. RD05, RD15, GD05, GD15, BD05, BD15 are the
MSBs. RD00, RD10, GD00, GD10, BD00, BD10 are the LSBs. If a 2-pixel data set is on
the data on
×
D0 is displayed first. In input/output modes 1 and 2, outputs RD1[0:5], GD1[0:5] and
BD1[0:5] are low.
In 3-bit data output mode: RD03, RD13, GD03, GD13, BD03, BD13 are the LSBs. RD0[2:0], RD1[2:0],
GD0[2:0], GD1[2:0], BD0[2:0], BD1[2:0] are low.
In 4-bit data output mode: RD02, RD12, GD02, GD12, BD02, BD12 are the LSBs. RD0[1:0], RD1[1:0],
GD0[1:0], GD1[1:0], BD0[1:0], BD1[1:0] are low.
In 3-bit data output mode: RD01, RD11, GD01, GD11, BD01, BD11 are the LSBs. RD0[0], RD1[0],
GD0[0], GD1[0], BD0[0], BD1[0] are low.
×
D0 and
×
D1,
RD1 [0:5]
44 to 47, 50, 51
O
GD0 [0:5]
34, 35, 38 to 41
O
GD1 [0:5]
26 to 28, 31 to 33
O
BD0 [0:5]
17, 20 to 23, 25
O
BD1 [0:5]
10, 11, 13 to 16
O
HSYNC
62
O
Vertical and horizontal synchronization signal outputs. To match the data signal timing, these outputs are
delayed with respect to their input signals. In input/output mode 0, they are delayed by 8 SCLK cycles,
and in input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, these
signals are output without being latched internally.
VSYNC
63
O
HDEN
64
O
Horizontal data valid-period signal output.To match the data signal timing, this output is delayed with
respect to the input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in
input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is
output without being latched internally.
CTL
70
O
LCD control signal output. To match the data signal timing, this output is delayed with respect to the
SCTL input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in input/output modes
1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is output without being
latched internally.
PWRSV
84
I
Power-save control input. When this input goes high, the internal clock stops and the LSI enters power-
save mode. Output data are held high. VSYNC, HSYNC, HDEN and CTL control signals, and either CLK
or CLKB are output without being latched internally. Tie low or leave open for normal operation.
BYPASS
85
I
Gray-scale processing bypass pin. When high, the input signals are latched and output without change.
When a high-level input on this pin is sampled on the falling edge of SCLK: in input/output mode 0, output
is delayed by 8 SCLK cycles, and in input/output modes 1 and 2, output is delayed by 16 SCLK cycles.
TEST [0:3]
4 to 7
I
Test pins [0:3]; left open for normal operation
NC
71
–
Must be left open.
Symbol
Pin No.
I/O
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC126A | QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS |
| LC151X01 | 15.1 Title XGA TFT LCD |
| LC151X01-C3 | 15.1 Title XGA TFT LCD |
| LC1611 | RES,475 OHM,1%,1/8W, |
| LC1622 | 16 characters x 2 lines |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC11021 | 制造商:Square D by Schneider Electric 功能描述:CIRCUIT BREAKER SHUNT TRIP 120-240V AC |
| LC11027 | 制造商:Square D by Schneider Electric 功能描述:CIRCUIT BREAKER SHUNT TRIP 24V DC |
| LC11039 | 制造商:Schneider Electric 功能描述:CIRCUIT BREAKER SHUNT TRIP 12V DC |
| LC1107AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC110A | 制造商:Microsemi Corporation 功能描述:TVS SGL UNI-DIR 110V 1.5KW 2PIN DO-13 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。