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參數(shù)資料
| 型號(hào)： | LC11011-141 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Computer Image Signal Processing Full-Color Gray-Scale Processor |
| 中文描述： | 計(jì)算機(jī)圖像信號(hào)處理全彩色灰度處理器 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 148K |
| 代理商： | LC11011-141 |
No. 5041-6/7
LC11011-141
Continued from preceding page.
Timing Chart
Symbol
Pin No.
I/O
Function
Red, green and blue gray scale data output pins. These are delayed by 2 clock cycles with respect to the
input data.
RDATA7, GDATA7 and BDATA7 are the MSBs.
In modes 0, 8, C and F, RDATA5, GDATA5 and BDATA5 are the LSBs. In these modes, RDATA [0:4],
GDATA [0:4] and BDATA [0:4] are not used.
In modes 1, 5, 9 and D, RDATA4, GDATA4 and BDATA4 are the LSBs. In these modes, RDATA [0:3],
GDATA [0:3] and BDATA [0:3] are not used.
In modes 6 and E, RDATA3, GDATA3 and BDATA3 are the LSBs. In these modes, RDATA [0:2],
GDATA [0:2] and BDATA [0:2] are not used.
In modes 3 and 7, RDATA2, GDATA2 and BDATA2 are the LSBs. In these modes, RDATA [0:1],
GDATA [0:1] and BDATA [0:1] are not used.
RDATA [0:7]
11 to 14, 16 to 19
Output
GDATA [0:7]
36 to 39, 42 to 45
Output
BDATA [0:7]
47 to 50, 52 to 55
Output
Vsync
27
Output
Horizontal and vertical synchronization signal outputs. To match the data signal timing these are delayed
by two clock cycles with respect to their input signals.
Hsync
29
Output
HDEN
25
Output
Horizontal data valid period signal output
CLT0
22
Output
LCD control signal outputs. To match the data signal timing these are delayed by two clock cycles with
respect to the SCTL [0:1] input signals.
CLT1
23
Output
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