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參數(shù)資料
| 型號： | LB1814M |
| 元件分類： | 運動控制電子 |
| 英文描述： | DISK DRIVE MOTOR CONTROLLER, 1 A, PDSO36 |
| 封裝： | 0.375 INCH, MFP-36 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 162K |
| 代理商： | LB1814M |
LB1814M
No.5198-12/13
5. External capacitors
(1) C1 and C2
C1 is required for VCC stabilization and C2 for constant-voltage power supply stabilization. A constant-voltage
power supply is also used within the IC chip circuits. It is stabilized by a capacitor (C2 with a capacitance of
approx 0.1
F). Select a capacitance for C1 at which the voltage fluctuations by the motor drive current are
stabilized. Noise has an adverse effect on both the VCC and constant-voltage power supplies so adequate
stabilization measures need to be provided. C1 and C2 must be connected near the VCC pin and VREG pin of the
IC and connected to the ground pin with a trace as short as possible.
(2) C7
The capacitance value of C7 serves to adjust the stop characteristics of the motor in the brake mode. To have the
motor switched from the decelerated state to a full stop state smoothly when brake is on, it is necessary to select
its capacitance value that is appropriate for the motor in use (approx. 0.001 to 0.01
F). If a slight reverse rotation
tends to occur after the motor decelerates and almost halts, increase the capacitance value of C7. On the other
hand, if a slight forward rotation tends to occur, decrease the capacitance value of C7.
This IC switches between the forward and reverse torques when the output is off whereby preventing through
current from occurring when switching the torque. C7 is also used to determine the output off period. The output
off time which occurs when switching between the forward and reverse torque modes is one period of BC
oscillation. Since the switching between the forward and reverse torque modes occurs when shifting the motor
into the constant speed mode or brake mode, too great a capacitance will increase the output off time, which
adversely affects on the performance of shifting the motor into the constant speed mode or brake mode.
(3) C8, C9 and C10
The Hall signals are used for the speed control, braking, forward/reverse logic circuits, etc. If noise immunity
poses problems in noise evaluation, connect a capacitor of approx. 0.01
F between the Hall input pins IN+ and
IN- .
(4) C11
C11 is a the AGC (Automatic Gain Control) pin smoothing capacitor. The AGC pin outputs the three-phase Hall
signal envelope, and is smoothed with a capacitor of approx. 0.1
F since it has ripple.
The capacitor C11 at the AGC pin is also used to generate the initial reset pulse to the IC internal logic circuit.
The initial reset pulse is generated when the S/B pin is placed in the start mode and is held on till the AGC pin
voltage (capacitor voltage) goes up to 1.0V. There are times when the LD pin is momentarily turned on at start
time if the initial reset is not active. The capacitor C11 at the AGC pin is discharged in the power save mode
(motor stopped and the SD pin is held on). In a mode in which the start and brake cycles alternate, if a restart is
attempted after a brake is applied and before the motor stops (power save mode established), no initial reset pulse
will be generated because the C11 is then not discharged. In such a case, the LD pin is likely to turn on
momentarily at start time. In an application in which the start and brake cycles need to alternate, it is necessary to
allow a power save time (discharging time of 10 ms or longer with a 0.1 F capacitor).
6. Pins X1 and X2
A crystal oscillator and a capacitor are normally connected to the X1 and X2 pins of this IC. The authorization of the
oscillator manufacturer must be obtained when selecting the oscillator and capacitor to be connected externally to
avoid the problem.
When using an external input signal (CLK) without using a crystal oscillator element, connect a 13k
resistor to the
X1 pin in series. In this case, the X2 pin must be held open.
fCLK=10 MHz (max.)
Input signal level range
Low-level voltage: 0.0V to 0.8V
High-level voltage: 2.5V to 5.0V
When using the external clock mode (setting the N pin to the Medium-level, no frequency division), connect the
external clock (EXT.CLK) to the X1 pin through a 13k
resistor which is connected in series. In this case, the X2
pin must be held open.
fEXT.CLK=10kHz (max.) (pattern FG mode)
Input signal level range
Low-level voltage: 0.0V to 0.8V
High-level voltage: 2.5V to 5.0V
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