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參數(shù)資料
| 型號： | L98SI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Octal Serial Solenoid Driver(八串行螺線管驅(qū)動器) |
| 中文描述： | 八路系列電磁驅(qū)動器（八串行螺線管驅(qū)動器） |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 77K |
| 代理商： | L98SI |
shiftregister(intotheSI pinandout theSOpin),al-
lowingtheotherSPIdevicesto becascadedinadai-
sychain with the L98SI.
CELow to High Transition
Once the last data bit has been shifted into the
L98SI,the CE pinshouldbe pulledhigh.
Attherising edgeof CEthe shiftregisterdataislat-
chedintotheparallellatchandtheoutputstageswill
beactuatedbythe newdata.Aninternal160
μ
s de-
laytimer will also be startedat thisrisingedge (see
t
UD
). During the 160
μ
s period, the outputs will be
protectedonlybytheanalogcurrentlimiting circuits
since the resetting of the parallel latches by faults
conditionswillbeinhibitedduringthisperiod.Thisal-
lowsthe part to overcomeany high inrushcurrents
that may flow immediately after turn on. Once the
delay period has elapsed, the output voltages are
sensedbythecomparatorsandanyoutputwithvol-
tageshigherthan1.8VarelatchedOFF.Itshouldbe
notedthatthe SCLK pinshouldbe lowatbothtran-
sitions of the CE pin to avoid any false clocking of
theshiftregister.TheSCLKinputisgatedbytheCE
pin, so that the SCLK pin is ignored whenever the
CE pinis high.
FAULTCONDITIONSCHECK
Checkingforfaultconditionsmaybedoneinthefol-
lowing way. Clock in a new control byte. Wait 160
microseconds or so to allow the outputs to settle.
Clockinthesamecontrolbyteandobservethediag-
nostic datathat comes out of thedevice.The diag-
nostic bits should be identical to the bits that were
firstclockedin.Anydifferenceswouldpointtoa fault
on thatoutput.If theoutputwasprogrammedONby
clockingina zero,anda one camebackas thedia-
gnosticbitforthatoutput,theoutputpinwasstillhigh
anda shortcircuit oroverloadconditionexists.Ifthe
outputwasprogrammedOFF byclocking in a one,
and a zerocameback as the diagnosticbit for that
output,nothinghadpulledtheoutputpinhighandit
Figure 1
: Byte Timing with AsynchronousReset.
L98SI
6/9
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