參數(shù)資料
型號(hào): L9733XP
廠商: 意法半導(dǎo)體
英文描述: Octal self configuring Low/High side driver
中文描述: 八路自我配置低/高邊驅(qū)動(dòng)器
文件頁數(shù): 21/33頁
文件大小: 466K
代理商: L9733XP
L9733
Serial Peripheral Interface (SPI)
21/33
5.4
Serial Clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100k
resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
5.5
Initial Input Command Register & Fault Register SPI Cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off , the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
5.6
Input Command Register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in table 9. Additional DI data will continue to be wrapped around to the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Table 8.
Bit Command Register Definition
Key Word
Writing Mode: Output
Output Status
MSB
LSB
1
0
1
0
1
1
0
0
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key Word
Writing Mode: Diag
Driver Diag Mode
MSB
LSB
1
0
1
0
0
0
1
1
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Key Word
Writing Mode: Protect
Driver Overcurrent Protection
MSB
LSB
1
0
1
0
1
0
1
0
Ilim 8 Ilim 7 Ilim 6
Ilim 5
Ilim 4
Ilim 3
Ilim 2
Ilim 1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
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