參數(shù)資料
型號(hào)： L6919CD
廠商： STMICROELECTRONICS
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 200 kHz SWITCHING FREQ-MAX, PDSO28
封裝： SO-28
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 558K
代理商： L6919CD
15/32
L6919C
OUTPUT VOLTAGE MONITOR AND PROTECTIONS
The output voltage is monitored by pin VSEN. If it is not within ±12% (Typ.) of the programmed value, the power
good output is forced low. Power good is an open drain output and it is enabled only after the soft start is finished
(2048 clock cycles after start-up).
The device provides over voltage protection; when the voltage sensed by the VSEN pin reaches 1.976V (typ.),
the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets
in order to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and
on is required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold
(set at 1.976V) and the reference programmed by VID.
Under voltage protection is also provided. If the output voltage drops below the 70% of the reference voltage for
more than one clock period the device turns off and the FAULT is driven high.
Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than VOUT reaches
0.8V). During soft-start the reference voltage used to determine the UV threshold is the increasing voltage driv-
en by the 2048 soft start digital counter.
REMOTE VOLTAGE SENSE
A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the re-
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR
is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors.
If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output
voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage.
INPUT CAPACITOR
The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as
reported in figure 10. Considering the dual-phase topology, the input RMS current is highly reduced comparing
with a single phase operation.
Figure 10. Input RMS Current vs. Duty Cycle (D) and Driving Relationships
OVP %
[]
1.976V
Re feren ceVo ltage VID
()
-----------------------------------------------------------------------
100
=
0.50
0.75
0.25
0.50
0.25
Single Phase
Dual Phase
Duty Cycle (VOUT/VIN)
R
m
s
Cu
rr
ent
Nor
m
al
iz
ed
(I
RM
S
/I
OU
T
)
>
<
=
0.5
D
if
D)
2
(2
1)
-
(2D
2
OUT
I
5
.
0
D
if
D)
2
(1
2D
2
OUT
I
rms
I
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