
10
L64015 VMI Bridge
LRCLK
Decoder Audio Left/Right Clock
Input
Using the default setting, LRCLK is driven HIGH when
the ASDATA pin has a right channel sample, and LRCLK
is driven LOW when the ASDATA pin has a left channel
sample.
PD[7:0]
Decoder Pixel Data [7:0]
Input
The PD[7:0] bus carries the pixel data for the recon-
structed pictures. The pixel data is formatted in ITU_R
BT.601 YCbCr chromaticity.
RD/WR_N
Decoder Read/Write
Output
The L64015 drives this signal HIGH for a read cycle or
drives it LOW for a write cycle. The L64015 also asserts
the chip select signal (CS_N) during a write or read cycle.
RST_N
Decoder Reset
Output
When the L64015 asserts RST_N, the L64020 resets its
internal microcontroller, FIFO controllers, state machines,
and registers. The minimum reset pulse width is 8 CLK27
cycles (SYSCLK). Both CLK27 and ACLK must be run-
ning during reset.
VREQ_N
Decoder Video Request
Input
The DVD Decoder asserts VREQ_N when it is ready to
receive a new byte of coded audio data in A/V PES
stream mode. The decoder is ready when the channel
FIFO is not near full. VREQ_N is not used in program
stream modes.
VS_N
Decoder Vertical Sync
Output
VS_N is the vertical sync signal to both the DVD Decoder
and the NTSC/PAL Encoder.
VVALID_N
Decoder Valid Video
Output
The L64015 asserts this signal in response to VREQ_N
if there is a valid data byte on the AD[8:0] bus. The
L64020 inputs the byte when it deasserts VREQ_N.
WAIT_N
Decoder Wait
Input
The L64020 asserts WAIT_N to indicate that its Host
Interface is busy with a read or write bus cycle and deas-
serts it when the current cycle is completed. WAIT_N is
3-stated when CS_N is not active.