L64005 MPEG-2 Audio/Video Decoder Technical Manual
8-23
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
The external host microprocessor maintains two PTS tables: one for
video and one for audio.
Figure 8.11 shows typical structure of the audio
and video PTSs and channel write pointer list. The host processor can
maintain the list as a software circular FIFO with read and write indices.
Figure 8.11
List of Pending PUs for
Video and Audio
8.5.3
Picture Header
Interrupt and
AUX FIFO
Interrupt
The picture start code interrupt indicates when a picture in the channel
buffer starts decoding. Note that the L64005 actually starts decoding the
picture on a PU boundary, which is determined by the vertical sync inter-
val. When the host processor receives the picture start code interrupt, it
reads the Picture Start Code Read Address register (Group 7, Registers
40-42). A xed 48-word difference may be subtracted from the start code
address to compensate for the internal channel FIFO size. The host pro-
cessor then searches the PTSs list for a write pointer that is less than or
equal to the calculated start code address. If such a write pointer is
found, then the PTS associated with that write pointer indicates the cor-
rect presentation time for the picture that caused the interrupt. The host
processor should invalidate the entry in the PTSs list, in order to avoid
incorrectly using it twice. During the search, it should have invalidated all
PTSn
Write Pointer n
PTSn+1
Write Pointer n+1
PTSn+2
Write Pointer n+2
PTSn+3
Write Pointer n+3
PTSn+m
Write Pointer n+m
The Video PTS List
33-bit
22-bit
PTSn
Write Pointer n
PTSn+1
Write Pointer n+1
PTSn+2
Write Pointer n+2
PTSn+3
Write Pointer n+3
PTSn+m
Write Pointer n+m
The Audio PTS List
33-bit
22-bit
.