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參數(shù)資料
| 型號： | L6256 |
| 廠商： | 意法半導體 |
| 英文描述： | 12V COMBO |
| 中文描述： | 12V的組合 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 258K |
| 代理商： | L6256 |
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Read and write clock rates may differ by as much
as 2:1. Clock rates may differ between different
chips using the bus.
A logic inversion may be used by other chips on
the bus. If this is done, use of the chip select line
after transmissions to the other chips is manda-
tory.
Chip Select
The external chip select masks out any incoming
data. When inactive, the serial port bit clocking
state machine is cleared, providing a resync
mechanism. The chip select may not change
states between every packet transmission, so it
should not be counted on as a continuous signal.
If the Dolphin is the only chip on the serial port,
the chip select will only be used an emergency re-
sync if the chip doesn’t answer queries.
Figure 5. Serial Port Chip Select Operation.
If an address byte is received that is not ad-
dressed to the Dolphin while chip select is active,
the Dolphin will ignore the transmission.
A metal option in the chip select circuit will allow
for either polarity of active level. Present intention
is for an active high level on the chip select pin.
Logic Inversion on Serial Port
If a logic inversion is used by other chips on the
serial bus, the R/W bit will assume the wrong
state and the Dolphin state mechanism will lose
synchronization. In this situation, it will be manda-
tory for the processor to deassert the chip select
to mask the serial port data intended for the other
chip.
Typical bus waveforms are shown below, with the
resultant activity.
SCLK
SDIO
CSELB
A1
D
A2
D
wrong
address
1) Block Mode Write - To other chip
(A1 and A2 ignored)
2) Valid Writes to L6256
SCLK
SDIO
CSELB
A1
D
A2
D
B
(All Data Written)
D97IN588
L6256
11/28
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