參數(shù)資料
型號(hào): L6205D
廠(chǎng)商: 意法半導(dǎo)體
英文描述: DMOS DUAL FULL BRIDGE DRIVER
中文描述: 偶的DMOS全橋驅(qū)動(dòng)器
文件頁(yè)數(shù): 8/21頁(yè)
文件大小: 388K
代理商: L6205D
L6205
8/21
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6205 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.3ohm (typical value @ 25°C), with intrinsic
fast freewheeling diode. Cross conduction protection
is achieved using a dead time (td = 1
μ
s typical) be-
tween the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figure 3. Charge Pump Circuit
LOGIC INPUTS
Pins IN1
A
, IN2
A
, IN1
B
and IN2
B
are TTL/CMOS and
μ
C compatible logic inputs. The internal structure is
shown in Fig. 4. Typical value for turn-on and turn-off
thresholds
are
respectively
Vthoff=1.3V.
Pins EN
A
and EN
B
have identical input structure with
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The EN
A
and EN
B
in-
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
Vthon=1.8V
and
(collector) structure, a pull-up resistor R
EN
and a ca-
pacitor C
EN
are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
R
EN
and the capacitor C
EN
are connected as shown
in Fig. 6. The resistor R
EN
should be chosen in the
range from 2.2k
to 180K
. Recommended values
for R
EN
and C
EN
are respectively 100K
and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 4. Logic Inputs Internal Structure
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
TRUTH TABLE
X
High Z = High Impedance Output
= Don't care
C
BOOT
C
P
R
P
D1
D2
220nF
10nF
100
1N4148
1N4148
D2
C
BOOT
D1
R
P
C
P
V
S
VS
A
VCP
VBOOT
VS
B
D01IN1328
INPUTS
IN1
X
L
H
L
H
OUTPUTS
OUT1
High Z
GND
Vs
GND
Vs
EN
L
H
H
H
H
IN2
X
L
L
H
H
OUT2
High Z
GND
GND
Vs
Vs
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
R
EN
C
EN
EN
A
or EN
B
D02IN1349
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
D02IN1350
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