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參數(shù)資料
| 型號(hào)： | L6180DPLCC28 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP CER 10000PF 50V Y5V 0805 |
| 中文描述： | 八進(jìn)制線路接收器 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | L6180DPLCC28 |
INPUT BALANCE MEASUREMENT
The balance of the receiver input voltage-current
characteristics and bias voltages shall be such
that the receiver will remain in theintendedbinary
state when a differential voltage Vi of 400mV is
appliedthrough 500
±
1% to each input terminal,
as shown above, and Vcm is varied between -7
and +7V.
When the polarity of Vi is reversed, the opposite
binary state shall be maintained under the same
conditions. Maintain input balance with input B
common with another receiver.
The voltage input (V
IN
) rejection is checked at the
center point between the High Operating Thresh-
old (V
th2
) and the Low OperatingThreshold(V
th1
)
Figure7:
Receiverinput Balance Measurement
Figure 8
: High FrequencySignalRejection
L6180 - L6181
7/10
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