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參數(shù)資料
| 型號： | L6000 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SINGLE CHIP READ & WRITE CHANNEL |
| 中文描述： | 單芯片讀 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 279K |
| 代理商： | L6000 |
DATA SEPARATOR DYNAMIC CHARACTERISTICS AND TIMING
(Continued)
Symbol
TAS, TAH
TPAMD
TD
Write Mode
TWD
Parameter
Test Condition
Min.
13
–
0.8TD
Typ.
Max.
–
±
15
1.2TD
Unit
ns
ns
ns
AMD Set Up and Hold Time
AMD Propagation Delay
1/3 Cell Delay
(**)
(**)
TD = 1/FSOUT,RR = 39K
(***)
Write Data Pulse Width
1.5V
CL
≤
15pF
0.8V to 2.0V,CL
≤
15pF
2.0V to 0.8V,CL
≤
15pF
0.8V to 2.0V,CL
≤
15pF
2.0V to 0.8V,CL
≤
15pF
2TFout/3
– 5
–
–
–
–
5
5
2TFout/3
+ 5
9
5
10
8
–
–
ns
TRWD
TFWD
TRWC
TFWC
TSNRZ
THNRZ
TPC
Write Data Rise Time
Write Data Fall Time
Write Data Clock Rise Time
Write Data Clock Fall Time
NRZ Set Up Time
NRZ Hold Time
Precompensation Time Shift
Magnitude Accuracy
ns
ns
ns
ns
ns
ns
TPCO = 0.04TREF
TPC(max) = 0.28TREF
TPC = nTPCO
n =0
1
≤
n
≤
7
– 0.5
n(0.8TPCO)
– 0.5
+ 0.5
n(1.2TPCO)
+0.5
ns
ns
Data Synchronization
TVCO
VCO CenterFrequency Period
FLTR2-FLTR2 = 0
TO = (8.95 + 0.786 x DR)
-1
,
RR = 39k
(***)
–1.5
≤
FLTR-FLTR2
≤
+1.5
(***)
ω
o =2
Π
T
VCO
–1.5
≤
FLTR-FLTR2
≤
+1.5
Read: KD = 0.7 + 0.43
x
DR,
PLL REF = RD 3T Pattern, Non-
Read: KD = 0.7+ 0.43
x
DR,
PLLREF = Fout / 2
(***)
0.9TO
1.1TO
ns
VCO Frequency Dynamic range
VCO Control Gain
±
25
±
45
%
KVCO
0.14Wo
0.26Wo rad/(Vxs)
KD
Phase Detector Gain
0.83KD
1.17KD
A/rad
KVCO x KD Product Accuracy
VCO PhaseRestart Error
Decode Window Cent. Accuracy
Decode Window Width
– 28
–
–
+ 28
4
±
1.5
–
%
ns
ns
ns
2TORC/3
- 1.5
SERIALPORT TIMING
Symbol
Tc
Tck1
TcKh
Tsens
Tsenh
Parameter
Test Condition
Min.
100
40
40
35
100
Typ.
Max.
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
SERIAL CLOCK+ Data Clock Period
SERIAL CLOCK+ Low Time
SERIAL CLOCK+ High Time
Enable to Clock Delay Time
Clock toDisable Delay Time
Delay from SERIAL
CLOCK+ falling edge
Tds
Tdh
Data Setup Time
Data Hold Time
Clock toValid Data Delay Time
15
15
–
–
–
27
ns
ns
ns
Tdskewl
Delay from SERIAL
CLOCK+ falling edge
Tdskewe
Tsendl
End of Valid Data to Clock
Time to Tri-stated SERIAL DATA I/O
–
–
0
50
ns
ns
Delay from falling edge
of SERIAL ENABLE
Tturnd
Tsl
SERIAL DATA I/O Turnaround Time
SERIAL ENABLE Low Time
70
200
–
–
ns
ns
(**)
Bench test only.
(***)
Preliminary data.
L6000
13/24
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