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參數(shù)資料
| 型號： | L573AQ1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCH |
| 中文描述： | 八路透明D類鎖存 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 191K |
| 代理商： | L573AQ1 |
SCAS714A SEPTEMBER 2003 REVISED MAY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Qualification in Accordance With
AEC-Q100
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t
pd
of 6.9 ns at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Contact factory for details. Q100 qualification data available on
request.
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
I
off
Supports Partial-Power-Down Mode
Operation
description/ordering information
The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V
CC
operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40
°
C to 125
°
C
SOIC DW
TSSOP PW
Reel of 2000
Reel of 2000
SN74LVC573AQDWRQ1
SN74LVC573AQPWRQ1
L573AQ1
L573AQ1
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
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