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參數(shù)資料
| 型號(hào)： | KSZ9021RLI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 52/58頁(yè) |
| 文件大小： | 0K |
| 描述： | TXRX ETHERNET GB RGMII 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 64-E-LQFP |
| 包裝： | 托盤(pán) |
| 其它名稱： | 576-3636 KSZ9021RLI-ND |
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MCP444X/446X
DS22265A-page 56
2010 Microchip Technology Inc.
6.2.4
ADDRESSING
The address byte is the first byte received following the
START condition from the master device. The address
contains four (or more) fixed bits and (up to) three user
defined hardware address bits (pins A1 and A0). These
7-bits address the desired I2C device. The A6:A2
address bits are fixed to “01011” and the device
appends the value of following two address pins (A1
and A0).
Since there are address bits controlled by hardware
pins, there may be up to four MCP44XX devices on the
same I2C bus.
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write (R/W) bit. Table 6-2 shows the fixed address for
device.
Hardware Address Pins
The hardware address bits (A1, and A0) correspond to
the logic level on the associated address pins. This
allows up to eight devices on the bus.
These pins have a weak pull-up enabled when the VDD
< VBOR. The weak pull-up utilizes the “smart” pull-up
technology and exhibits the same characteristics as the
High-voltage tolerant I/O structure.
The state of the A0 address pin is latch on POR/BOR.
This is required since High Voltage commands force
this pin (HVC/A0) to the VIHH level.
FIGURE 6-9:
Slave Address Bits in the
I2C Control Byte.
TABLE 6-2:
DEVICE SLAVE ADDRESSES
6.2.5
SLOPE CONTROL
The MCP44XX implements slope control on the SDA
output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
Device
Address
Comment
MCP44XX ‘0101 1’b + A1:A0
Supports up to 4
devices. (Note 1)
Note 1:
A0 is used for High-Voltage commands
(HVC/A0) and the value is latched at
POR/BOR.
S A6A5 A4 A3A2 A1 A0 R/W
A/A
Start
bit
Slave Address
R/W bit
A bit (controlled by slave device)
R/W
= 0 = write
R/W
= 1 = read
A
= 0 = Slave Device Acknowledges byte
A
= 1 = Slave Device does not Acknowledge byte
“0” “1” “0” “1”
See Table 6-2
“1”
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