參數(shù)資料
型號： KSZ8895RQI
廠商： Micrel Inc
文件頁數(shù)： 117/119頁
文件大?。?/td> 0K
描述： IC 10/100-T 5 PORT SW 128PQFP
標準包裝： 66
系列： *
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 97
PIC16(L)F1782/3
10.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F1782/3 has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF1782/3 operates at a maximum VDD of 3.6V
and does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be con-
nected to the VCAP pin for additional regulator stability.
The VCAPEN bit of Configuration Words determines if
which pin is assigned as the VCAP pin. Refer to
On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on the constant current rate, refer to the
LDO Regulator Characteristics Table in Section 30.0
TABLE 10-2:
SUMMARY OF CONFIGURATION WORD WITH LDO
TABLE 10-1:
VCAPEN SELECT BIT
VCAPEN
Pin
0
RA6
1
No VCAP
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
Register
on Page
CONFIG2
13:8
—
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
7:0
—
VCAPEN(1)
—
WRT<1:0>
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1:
Not implemented on PIC16LF1782/3.
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