參數(shù)資料
型號(hào)： KSZ8895MQ-EVAL
廠商： Micrel Inc
文件頁數(shù)： 84/119頁
文件大小： 0K
描述： BOARD EVALUATION FOR KSZ8895MQ
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8895MQ
已供物品： 板
相關(guān)產(chǎn)品： 576-3753-ND - IC ETHERNET SW 5PORT 128-PQFP
其它名稱： 576-3871
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Port Registers (Continued)
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Register 66 (0x42): Port 4 Control 2
Register 82 (0x52): Port 5 Control 2
Address
Name
Description
Mode
Default
7
User Priority Ceiling
1, If packet ‘s “user priority field” is greater than the
“user priority field” in the port default tag register,
replace the packet’s “user priority field” with the “user
priority field” in the port default tag register control 3.
0, no replace packet’s priority filed with port default tag
priority filed of the port register control 3 bit[7:5].
R/W
0
6
Ingress VLAN Filtering.
1, the switch will discard packets whose VID port
membership in VLAN table bit[11:7] does not include
the ingress port.
0, no ingress VLAN filtering.
R/W
0
5
Discard Non-PVID
packets
1, the switch will discard packets whose VID does not
match ingress port default VID.
0, no packets will be discarded.
R/W
0
4
Force Flow Control
1, will always enable Rx and Tx flow control on the
port, regardless of AN result.
0, the flow control is enabled based on AN result
(Default)
R/W
0
Strap-in option
LED1_1/PCOL For
port 3/port 4 LED1_1
default Pull up (1):
Not force flow
control; PCOL default
Pull-down (0): Not
force flow control.
LED1_1 Pull down
(0): Force flow
control; PCOL Pull-
up (1): Force flow
control. Note:
LED1_1 has internal
pull-up; PCOL have
internal pull-down.
3
Back Pressure Enable
1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure.
R/W
Pin PMRXD2 strap
option. Pull-down (0):
disable back
pressure. Pull-up(1):
enable back
pressure. Note:
PMRXD2 has internal
pull-down.
2
Transmit Enable
1, enable packet transmission on the port.
0, disable packet transmission on the port.
R/W
1
Receive Enable
1, enable packet reception on the port.
0, disable packet reception on the port.
R/W
1
0
Learning Disable
1, disable switch address learning capability.
0, enable switch address learning.
R/W
0
Note:
Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section.
March 12, 2014
67
Revision 1.7
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