參數(shù)資料
型號(hào): KSZ8842-16MQL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 112/141頁(yè)
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-16MQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-16MQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T,管理型
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁(yè)面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MQLA6-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1479-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1478-5-ND - IC SWITCH 10/100 16BIT 128PQFP
其它名稱: 576-1634
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Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
72
M9999-102207-1.9
Bank 18 Receive Byte Counter Register (0x06): RXBC
This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive
Frame in the RXQ.
Bit
Default Value
R/W
Description
15-11
-
RO
Reserved
10-0
-
RO
RXBC Receive Byte Count
Receive Byte Count.
Bank 19 Multicast Table Register 0 (0x00): MTR0
The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from
CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four
registers to be used, while the others determine which bit within the register.
Multicast table register 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
MTR0 Multicast Table 0
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR,
all multicast addresses are received regardless of the multicast table value.
Bank 19 Multicast Table Register 1 (0x02): MTR1
Multicast table register 1.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
MTR0 Multicast Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR,
all multicast addresses are received regardless of the multicast table value.
Bank 19 Multicast Table Register 2 (0x04): MTR2
Multicast table register 2.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
MTR0 Multicast Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR,
all multicast addresses are received regardless of the multicast table value.
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