參數(shù)資料
型號(hào): KSZ8841-16MBL
廠商: Micrel Inc
文件頁數(shù): 61/105頁
文件大?。?/td> 0K
描述: IC MAC CTLR 1PORT ETH 100-LBGA
標(biāo)準(zhǔn)包裝: 260
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3075
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
59
M9999-102207-1.6
Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3
This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 0. Setting bit 15 selects the 64th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0
RW
WF0BM3
Wake-up Frame 0 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 0 pattern.
Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0
RW
WF1CRC0
Wake-up frame 1 CRC (lower 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0
RW
WF1CRC1
Wake-up frame 1 CRC (upper 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0
This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte
of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1.
Bit
Default Value
R/W
Description
15-0
0
RW
WF1BM0
Wake-up frame 1 Byte Mask 0.
The first 16 bytes mask of a Wake-up frame 1 pattern.
Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1.
Bit
Default Value
R/W
Description
15-0
0
RW
WF1BM1
Wake-up frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 1 pattern.
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