KS8721B/BT Micrel, Inc. Pin Number Pin Name Type(Note 1)
參數(shù)資料
型號： KSZ8721BI
廠商： Micrel Inc
文件頁數(shù)： 30/32頁
文件大小： 0K
描述： IC TXRX PHY 10/100 2.5V 48SSOP
標準包裝： 30
類型： 收發(fā)器
驅動器/接收器數(shù)： 1/1
規(guī)程： MII，RMII
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 48-SSOP
包裝： 管件
產品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC
576-1626-ND - BOARD EVALUATION FOR KSZ8721BL
其它名稱： 576-1027
March 2006
7
M9999-030106
KS8721B/BT
Micrel, Inc.
Pin Number
Pin Name
Type(Note 1) Pin Function
25
INT#/
Ipu/O
Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up
PHYAD0
/reset. See “Strapping Options” section for details.
“Strapping Options”
22
CRS/
Ipd/O
MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB
RMII_BTB
during reset when RMII mode is selected. See “Strapping Options” section
“Strapping Options”
for details.
23
GND
Ground.
26
LED0/TEST
Ipu/O
Link/Activity LED Output:
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
The external pull-down enable test mode and only used for the factory test.
27
LED1/
Ipu/O
Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.
SPD100/
See “Strapping Options” section for details.
“Strapping Options”
noFEF
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
28
LED2/
Ipu/O
Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/
DUPLEX
reset. See “Strapping Options” section for details.
“Strapping Options”
Duplex
Pin State
LED Denition
Half
H
“off”
Full
L
“on”
29
LED3/
Ipu/O
Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN
reset. See “Strapping Options” section for details.
“Strapping Options”
Collison
Pin State
LED Denition
No Collision
H
“off”
Collision
L
“on”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0=Power down, Active low.
31
VDDRX
Pwr
Analog 2.5V power supply.
32
RX-
I
Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.
33
RX+
I
Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.
34
FXSD/FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See “100BT FX Mode” section for more details.
“100BT FX Mode”
35
GND
Ground.
36
GND
Ground.
Note 1. Pwr = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
NC = No connect
25
INT#/
Ipu/O
Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up
PHYAD0
/reset. See
22
CRS/
Ipd/O
MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB
RMII_BTB
during reset when RMII mode is selected. See
for details.
23
GND
Ground.
26
LED0/TEST
Ipu/O
Link/Activity LED Output:
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
The external pull-down enable test mode and only used for the factory test.
27
LED1/
Ipu/O
Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.
SPD100/
See
noFEF
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
28
LED2/
Ipu/O
Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/
DUPLEX
reset. See
Half
H
“off”
Full
L
“on”
29
LED3/
Ipu/O
Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN
reset. See
No Collision
H
“off”
Collision
L
“on”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0=Power down, Active low.
31
VDDRX
Pwr
Analog 2.5V power supply.
32
RX-
I
Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.
33
RX+
I
Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.
34
FXSD/FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See
35
GND
Ground.
36
GND
Ground.
Pin Number
Pin Name
Type
25
INT#/
Ipu/O
Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up
PHYAD0
/reset. See
22
CRS/
Ipd/O
MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB
RMII_BTB
during reset when RMII mode is selected. See
for details.
23
GND
Ground.
26
LED0/TEST
Ipu/O
Link/Activity LED Output:
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
The external pull-down enable test mode and only used for the factory test.
27
LED1/
Ipu/O
Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.
SPD100/
See
noFEF
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
28
LED2/
Ipu/O
Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/
DUPLEX
reset. See
Half
H
“off”
Full
L
“on”
29
LED3/
Ipu/O
Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN
reset. See
No Collision
H
“off”
Collision
L
“on”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0=Power down, Active low.
31
VDDRX
Pwr
Analog 2.5V power supply.
32
RX-
I
Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.
33
RX+
I
Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.
34
FXSD/FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See
35
GND
Ground.
36
GND
Ground.
Pin Number
Pin Name
Type
25
INT#/
Ipu/O
Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up
PHYAD0
/reset. See
22
CRS/
Ipd/O
MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB
RMII_BTB
during reset when RMII mode is selected. See
for details.
23
GND
Ground.
26
LED0/TEST
Ipu/O
Link/Activity LED Output:
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
The external pull-down enable test mode and only used for the factory test.
27
LED1/
Ipu/O
Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.
SPD100/
See
noFEF
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
28
LED2/
Ipu/O
Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/
DUPLEX
reset. See
Half
H
“off”
Full
L
“on”
29
LED3/
Ipu/O
Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN
reset. See
No Collision
H
“off”
Collision
L
“on”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0=Power down, Active low.
31
VDDRX
Pwr
Analog 2.5V power supply.
32
RX-
I
Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.
33
RX+
I
Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.
34
FXSD/FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See
35
GND
Ground.
36
GND
Ground.
Pin Function
25
INT#/
Ipu/O
Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up
PHYAD0
/reset. See
22
CRS/
Ipd/O
MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB
RMII_BTB
during reset when RMII mode is selected. See
for details.
23
GND
Ground.
26
LED0/TEST
Ipu/O
Link/Activity LED Output:
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
The external pull-down enable test mode and only used for the factory test.
27
LED1/
Ipu/O
Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset.
SPD100/
See
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
28
LED2/
Ipu/O
Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/
DUPLEX
reset. See
Half
H
“off”
Full
L
“on”
29
LED3/
Ipu/O
Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/
NWAYEN
reset. See
No Collision
H
“off”
Collision
L
“on”
30
PD#
Ipu
Power Down. 1 = Normal operation, 0=Power down, Active low.
31
VDDRX
Pwr
Analog 2.5V power supply.
32
RX-
I
Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT.
33
RX+
I
Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT.
34
FXSD/FXEN
Ipd/O
Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is
disable. The default is “0”. See
35
GND
Ground.
36
GND
Ground.
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
Lnk/Act
Pin State
LED Denition
No Link
H
“off”
Link
L
“on”
Act
—
“Toggle”
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
Speed
Pin State
LED Denition
10BT
H
“off”
100BT
L
“on”
Duplex
Pin State
LED Denition
Half
H
“off”
Full
L
“on”
Duplex
Pin State
LED Denition
Half
H
“off”
Full
L
“on”
Collison
Pin State
LED Denition
No Collision
H
“off”
Collision
L
“on”
Collison
Pin State
LED Denition
No Collision
H
“off”
Collision
L
“on”
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