參數(shù)資料
型號(hào): KSZ8041MNLU TR
廠商: Micrel Inc
文件頁(yè)數(shù): 2/54頁(yè)
文件大?。?/td> 0K
描述: TXRX PHY 100BASE TX 3.3V 32QFN
標(biāo)準(zhǔn)包裝: 1
類型: PHY 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 5/5
規(guī)程: MII,RMII
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 576-3744-6
Micrel, Inc.
KSZ8041NL/RNL
September 2010
10
M9999-090910-1.4
Pin Description – KSZ8041NL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
VDDPLL_1.8
P
1.8V analog VDD
3
VDDA_3.3
P
3.3V analog VDD
4
RX-
I/O
Physical receive or transmit signal (- differential)
5
RX+
I/O
Physical receive or transmit signal (+ differential)
6
TX-
I/O
Physical transmit or receive signal (- differential)
7
TX+
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII mode
is selected.
9
XI /
REFCLK
I
Crystal / Oscillator / External Clock Input
MII Mode:
25MHz +/-50ppm (crystal, oscillator, or external clock)
RMII Mode:
50MHz +/-50ppm (oscillator, or external clock only)
10
REXT
I/O
Set physical transmit output current
Connect a 6.49K
Ω resistor in parallel with a 100pF capacitor to ground on this pin.
See KSZ8041NL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7K
Ω pull-up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13
RXD3 /
PHYAD0
Ipu/O
MII Mode:
Receive Data Output[3]
(2)
/
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
14
RXD2 /
PHYAD1
Ipd/O
MII Mode:
Receive Data Output[2]
(2)
/
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
15
RXD1 /
RXD[1] /
PHYAD2
Ipd/O
MII Mode:
Receive Data Output[1]
(2)
/
RMII Mode:
Receive Data Output[1]
(3)
/
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
16
RXD0 /
RXD[0] /
DUPLEX
Ipu/O
MII Mode:
Receive Data Output[0]
(2)
/
RMII Mode:
Receive Data Output[0]
(3)
/
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
VDDIO_3.3
P
3.3V digital VDD
18
RXDV /
CRSDV /
CONFIG2
Ipd/O
MII Mode:
Receive Data Valid Output /
RMII Mode:
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
19
RXC
O
MII Mode:
Receive Clock Output
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