參數(shù)資料
型號(hào)： KS8995MA
廠商： Micrel Inc
文件頁(yè)數(shù)： 46/73頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 散裝
配用： 576-1017-ND - BOARD EVAL EXPERIMENT KS8995M
KS8995MA
Micrel, Inc.
M9999-051305
50
May 2005
Register 31 (0x1F): Port 1 Control 14
Register 47 (0x2F): Port 2 Control 14
Register 63 (0x3F): Port 3 Control 14
Register 79 (0x4F): Port 4 Control 14
Register 95 (0x5F): Port 5 Control 14
Address
Name
Description
Mode
Default
7
PHY Loopback
1, perform PHY loopback, i.e. loopback MAC’s Tx
R/W
0
back to Rx.
0, normal operation.
6
Remote Loopback
1, perform remote loopback, i.e. loopback PHY’s Rx
R/W
0
back to Tx.
0, normal operation.
5
PHY Isolate
1, electrical isolation of PHY from MII and Tx+/Tx-.
R/W
0
0, normal operation.
4
Soft Reset
1, PHY soft reset.
R/W
0
0, normal operation.
3
Force Link
1, Force link in the PHY.
R/W
0
0, normal operation.
2-1
Reserved
N/A
RO
0
Far End Fault
1, Far end fault status detected.
RO
0
0, no far end fault status detected.
Advanced Control Registers
The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used
to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into
64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register
bit is a 1, the priority is high; if the register bit is a 0, the priority is low.
Address
Name
Description
Mode
Default
Register 96 (0x60): TOS Priority Control Register 0
7-0
DSCP[63:56]
R/W
00000000
Register 97 (0x61): TOS Priority Control Register 1
7-0
DSCP[55:48]
R/W
00000000
Register 98 (0x62): TOS Priority Control Register 2
7-0
DSCP[47:40]
R/W
00000000
Register 99 (0x63): TOS Priority Control Register 3
7-0
DSCP[39:32]
R/W
00000000
Register 100 (0x64): TOS Priority Control Register 4
7-0
DSCP[31:24]
R/W
00000000
Register 101 (0x65): TOS Priority Control Register 5
7-0
DSCP[23:16]
R/W
00000000
Register 102 (0x66): TOS Priority Control Register 6
7-0
DSCP[15:8]
R/W
00000000
Register 103 (0x67): TOS Priority Control Register 7
7-0
DSCP[7:0]
R/W
00000000
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Register 104 (0x68): MAC Address Register 0
7-0
MACA[47:40]
R/W
0x00
Register 105 (0x69): MAC Address Register 1
7-0
MACA[39:32]
R/W
0x10
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