參數資料
型號: KMPC875ZT80
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數: 36/92頁
文件大?。?/td> 1499K
代理商: KMPC875ZT80
MPC885/MPC880 Hardware Specifications, Rev. 3
36
Freescale Semiconductor
Bus Signal Timing
Table 10
provides the interrupt timing for the MPC885/880.
Figure 25
provides the interrupt detection timing for the external level-sensitive lines.
Figure 25. Interrupt Detection Timing for External Level Sensitive Lines
Figure 26
provides the interrupt detection timing for the external edge-sensitive lines.
Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines
Table 10. Interrupt Timing
Num
Characteristic
1
1
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC885/880 is able to support.
All Frequencies
Unit
Min
Max
I39
IRQx valid to CLKOUT rising edge (setup time)
6.00
ns
I40
IRQx hold time after CLKOUT
2.00
ns
I41
IRQx pulse width low
3.00
ns
I42
IRQx pulse width high
3.00
ns
I43
IRQx edge-to-edge time
4
×
T
CLOCKOUT
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I41
I42
I43
I43
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