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    參數(shù)資料
    型號(hào): KMPC857DSLVR50B
    廠商: Freescale Semiconductor
    文件頁數(shù): 12/88頁
    文件大?。?/td> 0K
    描述: IC MPU POWERQUICC 50MHZ 357-PBGA
    標(biāo)準(zhǔn)包裝: 2
    系列: MPC8xx
    處理器類型: 32-位 MPC8xx PowerQUICC
    速度: 50MHz
    電壓: 3.3V
    安裝類型: 表面貼裝
    封裝/外殼: 357-BBGA
    供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
    包裝: 托盤
    MPC862/857T/857DSL PowerQUICC Family Hardware Specifications, Rev. 3
    2
    Freescale Semiconductor
    Overview
    1Overview
    The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC family of devices. It
    is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a
    variety of controller applications and communications and networking systems. The
    MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members
    of the MPC860 family.
    Table 1 shows the functionality supported by the members of the MPC862/857T/857DSL family.
    2Features
    The following list summarizes the key MPC862/857T/857DSL features:
    Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
    thirty-two 32-bit general-purpose registers (GPRs)
    — The core performs branch prediction with conditional prefetch, without conditional execution
    — 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
    – 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
    instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
    with 128 sets.
    – 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
    cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
    – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
    cache blocks.
    – Caches are physically addressed, implement a least recently used (LRU) replacement
    algorithm, and are lockable on a cache block basis.
    — MMUs with 32-entry TLB, fully associative instruction and data TLBs
    — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
    spaces and 16 protection groups
    — Advanced on-chip-emulation debug mode
    Table 1. MPC862 Family Functionality
    Part
    Cache
    Ethernet
    SCC
    SMC
    Instruction
    Cache
    Data Cache
    10T
    10/100
    MPC862P
    16 Kbyte
    8 Kbyte
    Up to 4
    1
    4
    2
    MPC862T
    4 Kbyte
    Up to 4
    1
    4
    2
    MPC857T
    4 Kbyte
    1
    2
    MPC857DSL
    4 Kbyte
    1
    1 1
    1
    On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does
    not support the Time Slot Assigner (TSA).
    1 2
    2
    On the MPC857DSL, the SMC (SMC1) is for UART only.
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