參數(shù)資料
型號： KMPC8560VTAQFB
廠商： Freescale Semiconductor
文件頁數(shù)： 2/36頁
文件大小： 0K
描述： IC MPU POWERQUICC III 783-FCPBGA
標準包裝： 2
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1.3V
安裝類型： 表面貼裝
封裝/外殼： 784-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
10
MPC8560 PowerQUICC III
MOTOROLA
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
e500 Core Overview
Two simple execution units that perform the following:
— Single-cycle add and subtract
— Single-cycle shift and rotate
— Single-cycle logical operations
— Supports integer signal processing operations
Multiple-cycle execution unit (MU)
— Four-cycle latency for integer and floating-point multiplication (including integer, fractional,
and both vector and scalar floating-point multiply instructions).
— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and SPFP divide
instructions. Note that the MU allows divide instructions to bypass the second two MU pipeline
stages, freeing those stages for other MU instructions to execute in parallel.
— Four-cycle floating-point multiply
— Four-cycle floating-point add and subtract
Signal processing engine APU (SPE APU). The SIMD capability provided by the 64-bit execution
units (MIU, LSU, SIU1) is not a separate execution unit. The hardware that executes 32-bit Book
E instructions also executes the lower half of 64-bit SPU instructions.
— Single-cycle integer add and subtract
— Single-cycle logical operations
— Single-cycle shift and rotate
— Four-cycle integer pipelined multiplies
— 4-, 11-, 19-, and 35-cycle integer divides
— Four-cycle single instruction multiple data (SIMD) pipelined multiply-accumulate (MAC)
— 64-bit accumulator for MAC operations
— Single-precision floating-point operations
Load/store unit (LSU)
— Three-cycle load latency
— Fully pipelined
— Four-entry load queue allows up to four load misses before stalling
— Can continue servicing load hits when load queue is full
— Six-entry store queue allows full pipelining of stores
Cache coherency
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— 60x-like address protocol with address pipelining and retry/copyback
— Two general-purpose read data, one write data bus
— 128-bit data plus parity/tags (each data bus)
— Supports out-of-order reads, in-order writes
— Little to no data bus arbitration logic required for native systems
— Easily adaptable to 60x-like environments
— Supports one-level pipelining of addresses with address-retry responses
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數(shù)
參數(shù)描述
KMPC8567CVTANGGA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
KMPC8567CVTANGJA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
KMPC8567CVTANJGA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
KMPC8567CVTANJJA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
KMPC8567CVTAQGGA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
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