參數(shù)資料
型號(hào): KMPC853TVR66A
廠商: Freescale Semiconductor
文件頁數(shù): 23/88頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC 166MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 166MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor
3
Features
General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— Seven port pins with interrupt capability
— Eighteen internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Eight serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Two baud-rate generators
— Independent (can be connected to any SCC3/4 or SMC1)
— Allow changes during operation
— Autobaud support option
Two SCCs (serial communication controllers)
— Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Universal asynchronous receiver transmitter (UART)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
SMC (serial management channels)
— UART
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