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參數(shù)資料
| 型號： | KMM966G512 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx64 SGRAM SODIMM(512Kx64 圖形RAM模塊) |
| 中文描述： | 512Kx64 SGRAM個SODIMM（512Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 148K |
| 代理商： | KMM966G512 |
SGRAM MODULE
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
KMM965G512BQ(P)N / KMM966G512BQ(P)N
ELECTRONICS
- 9 -
Rev. 2.5 (July. 1998)
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note :
Parameter
Symbol
Version
Unit
Note
-7
-8
-10
Row active to row active delay
t
RRD(min)
14
16
20
ns
1
RAS to CAS delay
t
RCD(min)
16
16
20
ns
1
Row precharge time
t
RP(min)
21
20
20
ns
1
Row active time
t
RAS(min)
49
48
50
ns
1
t
RAS(max)
100
us
Row cycle time
t
RC(min)
70
70
70
ns
1
Last data in to new col. address delay
t
CDL(min)
1
CLK
2
Last data in to row precharge
t
RDL(min)
1
CLK
2
Last data in to burst stop
t
BDL(min)
1
CLK
2
Col. address to col. address delay
t
CCD(min)
1
CLK
3
Block write data-in to PRE command delay
t
BPL(min)
1
CLK
Block write cycle time
t
BWC(min)
1
CLK
1, 3
Number of valid output data
CAS latency=3
2
CLK
4
CAS latency=2
1
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