參數(shù)資料
型號(hào): KMC7448VU1700LD
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 14/60頁(yè)
文件大?。?/td> 0K
描述: IC MPU 128BIT 1700MHZ 360-FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 1.7GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 360-CBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 360-FCCBGA(25x25)
包裝: 托盤
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
21
Electrical and Thermal Characteristics
5.2.3
IEEE Std. 1149.1 AC Timing Specifications
Table 10 provides the IEEE Std. 1149.1 (JTAG) AC timing specifications as defined in Figure 8 through
Table 10. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
033.3
MHz
TCK cycle time
tTCLK
30
ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
ns
TCK rise and fall times
tJR and tJF
—2
ns
TRST assert time
tTRST
25
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
ns
3
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
20
25
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
30
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 7).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
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