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參數(shù)資料
| 型號： | KM6164000BLT-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx16 bit Low Power CMOS Static RAM |
| 中文描述： | 256Kx16位低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | KM6164000BLT-7L |
KM6164000B Family
CMOS SRAM
Revision 4.01
June 1998
5
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
=50pF+1TTL
AC CHARACTERISTICS
(Vcc=4.5~5.5V, Commercial product : T
A=
0 to 70
°
C, Industrial product : T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
100ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
100
-
ns
Address access time
t
AA
-
55
-
70
-
100
ns
Chip select to output
t
CO
-
55
-
70
-
100
ns
Output enable to valid output
t
OE
-
25
-
35
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
5
-
ns
UB, LB enable to low-Z output
t
BLZ
5
-
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
25
0
30
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
0
30
ns
UB, LB disable to high-Z output
t
BHZ
0
20
0
25
0
30
ns
Output hold from address change
t
OH
10
-
10
-
10
-
ns
LB, UB valid to data output
t
BA
-
25
-
35
-
50
ns
Write
Write cycle time
t
WC
55
-
70
-
100
-
ns
Chip select to end of write
t
CW
45
-
60
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
80
-
ns
Write pulse width
t
WP
45
-
55
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
0
30
ns
Data to write time overlap
t
DW
25
-
30
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
ns
LB, UB valid to end of write
t
BW
45
-
60
-
-
80
ns
DATA RETENTION CHARACTERISTICS
1. Industrial Product : 20
μ
A
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
≥
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V
-
-
15
1)
-
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
ms
Recovery time
t
RDR
5
-
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM6164000BLTI-10L | 256Kx16 bit Low Power CMOS Static RAM |
| KM6164000BLTI-7L | 256Kx16 bit Low Power CMOS Static RAM |
| KM6164000BLI-L | 256Kx16 bit Low Power CMOS Static RAM |
| KM6164000B | 256Kx16 bit Low Power CMOS Static RAM |
| KM6164000BL-L | 256Kx16 bit Low Power CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM6164000BLTI-10L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx16 bit Low Power CMOS Static RAM |
| KM6164000BLTI-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx16 bit Low Power CMOS Static RAM |
| KM6164002 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
| KM6164002AJ-20 | 制造商:SEC 功能描述: |
| KM6164002E | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS SRAM |
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