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參數(shù)資料
| 型號(hào)： | KM416S4020B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 16Bit x 2 Banks Synchronous DRAM(2M x 16位 x2組同步動(dòng)態(tài)RAM) |
| 中文描述： | 200萬(wàn)× 16 × 2銀行同步DRAM（2米× 16位x2組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 1/43頁(yè) |
| 文件大?。?/td> | 597K |
| 代理商： | KM416S4020B |
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KM416S4020B
CMOS SDRAM
REV. 4 June '98
Revision History
Revision .1(November 1997)
- t
RDL
has changed 10ns to 12ns.
- Binning -10 does not meet PC100 characteristics .
So AC parameter/Characteristics have changed to 64M 2nd values.
Revision .2 (February 1998)
- Input leakage Currents (Inputs / DQ) are changed.
I
IL
(Inputs) :
±
5uA to
±
1uA, I
IL
(DQ) :
±
5uA to
±
1.5uA.
- The measuring condition of t
R
/t
F
is clearly defined each as
0pF +50
to V
SS
/V
DD
, 50pF +50
to V
SS
/V
DD
- Cin to be measured at V
DD
= 3.3V, T
A
= 23
°
C, f = 1MHz, V
REF
=1.4V
±
200 mV.
- AC Operating Condition is changed as defined :
V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
- I
CC3
PS is changed 1mA to 2mA.
- I
CC6
for Low power is changed 400uA to 450uA.
- I
CC4
value is changed.
Revision . 3 (March 1998)
- I
CC2
N, I
CC2
NS, I
CC3
N & I
CC3
NS values are changed.
Revision .4 (June 1998)
- t
SH
(-10 binning) is revised.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416S4020BT-GL | 制造商:Samsung Semiconductor 功能描述: |
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| KM416S4030CT-F10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S4030CT-F7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S4030CT-F8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit x 4 Banks Synchronous DRAM |
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