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參數(shù)資料
| 型號： | KL5KUSB200 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB2.0 Transceiver |
| 中文描述： | USB2.0接口收發(fā)器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 26K |
| 代理商： | KL5KUSB200 |
KL5KUSB200
1
Ver. 2.2
USB2.0 Transceiver
US: Kawasaki LSI , 2570 N. 1
st
Street, San Jose, CA 95131,Tel:(408) 570-0555, Fax(408) 570-0567,
www.klsi.com
Japan: Kawasaki Steel Corp, Makuhari Techno-Garden B5, Nakase 1-3, Mihama-ku, Chiba, 261-8501Tel:(043)296-3283, Fax:(043)296-3285, email:usb-info@lsidv.kawasaki-steel.co.jp
General Description
The Kawasaki USB 2.0 Compliant Transceiver is the interface between the high performance USB serial
bus and the 16-bit
SIE bus. The high-speed analog interface and the digital serial bit processing feature
of the USB 2.0 transceiver enables a highly integrated USB 2.0 device. The transceiver is controlled by
input signals from the SIE bus which is synchronized with the 30MHz clock output. The Kawasaki
Transceiver also provides output signals to monitor the USB bus status. The Kawasaki Transceiver, SIE,
and logic design are combined to create Kawasaki's USB chip solutions for peripheral devices or can be
used as IP with our ASIC technology.
Features
USB 2.0 compliant transceiver
UTMI based design (USB 2.0 Transceiver Macro
cell Interface)
Generates 48MHz to 480MHz input
Full Speed / High Speed capabilities
Supports “Chirp” for High Speed recognition
Support Reset and Suspend
Operational mode selection
Status signals for monitoring USB bus
Optional CRC verification/generation logic
Mode bit expansion for device test
16 bit Bi-directional SIE bus
TX data packet abort
ASIC IP supports High speed SIE with
ASIC IP
80 pin LQFP package (12 mm
2
)
Block Diagram
High Speed
Front end
SIE
Interface
Status
Control Signals
SIE_Data
Shared
Logic
Full Speed
Front end
DPLL
HS
DLL
EBUF
HSDM
HSDP
RPU_ENA
FSDP
FSDM
CKOUT
SIE Bus
USB Bus
Clock
Generator
External
48MHz Clk
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