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參數(shù)資料
| 型號： | KL5BUDV003 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB2.0 to PCI BUS |
| 中文描述： | USB2.0接口的PCI總線 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 131K |
| 代理商： | KL5BUDV003 |
Kawasaki LSI
2570 North First Street
Suite 301
San Jose, CA 95131
Tel: (408) 570-0555
Fax: (408) 570-0567
www.klsi.com
KL5BUDV003
4
Ver. 2.0
USB2.0 to PCI BUS
Pin Description (PCI Mode)
Pin #
QFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
I/O
Pin Name
Description
I
I
I
I
I
P_MODE[0]
P_MODE[1]
P_MODE[2]
TEST[0]
TEST[1]
VDD18
GND
AVDD
GND
AVDD
GND
REXT
RPU_ENA
AVDD
GND
GND
FSDP
HSDP
HSDM
FSDM
GND
GND
AVDD
VDD
GND
VDD18
GND
TEST[2]
TEST[3]
VDD
GND
INTAN
RSTN
CLK
GNTN
REQN
GND
AD[31]
AD[30]
AD[29]
VDD
GND
AD[28]
VDD18
GND
AD[27]
GND
Burst Length select flag
Burst Length select flag
Burst Length select flag
LSI shipment test input and mode pin
LSI shipment test input and mode pin
1.8V power pin
Ground
3.3V power pin
Ground
3.3V power pin
Ground
USB100uA fixed reference bias current pin
USB External pull up resistor source drive pin
3.3V power pin
Ground
Ground
USB FS_XVR DP pin
USB HS_XVR DP pin
USB HS_XVR DM pin
USB FS_XVR DM pin
Ground
Ground
3.3V power pin
3.3V power pin
Ground
1.8V power pin
Ground
LSI shipment test input and mode pin
LSI shipment test input and mode pin
3.3V power pin
Ground
PCI interrupt signal
PCI bus asynchronous reset input
PCI clock input
PCI bus grant signal
PCI bus request signal
Ground
PCI address data bus
PCI address data bus
PCI address data bus
3.3V power pin
Ground
PCI address data bus
1.8V power pin
Ground
PCI address data bus
Ground
--
--
--
--
--
--
O
O
--
--
--
I/O
I/O
I/O
I/O
--
--
--
--
--
--
--
I
I
--
--
O
I
I
I
O
--
I/O
I/O
I/O
--
--
I/O
--
--
I/O
--
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| KL5KUSB101-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB to Ethernet Controller |
| KL5KUSB105 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB to 4 Serial Ports |
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