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| 型號(hào)： | KIT33993DWBEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 26/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR MC33993 SWITCH DET |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 微控制器 |
| 適用于相關(guān)產(chǎn)品： | MC33993 |
| 所含物品： | 評(píng)估板、數(shù)據(jù)表和說(shuō)明文檔 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33993
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
ARCHIVE
INFORMATION
ARCHIVE
INFORMATION
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V
≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
tPULSE(ON)
15
16
20
ms
Interrupt Delay Time
Normal Mode
tINT-DLY
–
5.0
16
μs
Sleep Mode Switch Scan Time
tSCAN
100
200
300
μs
Calibrated Scan Timer Accuracy
Sleep Mode
tSCAN TIMER
–
10
%
Calibrated Interrupt Timer Accuracy
Sleep Mode
tINT TIMER
–
10
%
DIGITAL INTERFACE TIMING (11)
VPWR ≤ 0.2 V
tRESET
–
10
μs
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
tLEAD
100
–
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
tLAG
50
–
ns
SI to Falling Edge of SCLK
Required Setup Time
tSI(SU)
16
–
ns
Falling Edge of SCLK to SI
Required Hold Time
tSI(HOLD)
20
–
ns
SI, CS, SCLK Signal Rise Time (13)
tR(SI)
–
5.0
–
ns
SI, CS, SCLK Signal Fall Time (13)
tF(SI)
–
5.0
–
ns
Time from Falling Edge of CS to SO Low Impedance (14)
tSO(EN)
–
55
ns
Time from Rising Edge of CS to SO High Impedance (15)
tSO(DIS)
–
55
ns
Time from Rising Edge of SCLK to SO Data Valid (16)
tVALID
–
25
55
ns
Notes
11.
These parameters are guaranteed by design. Production test equipment uses a 4.16 MHz, 5.0 V SPI interface.
12.
This parameter is guaranteed by design but not production tested.
13.
Rise and Fall time of the incoming SI, CS, and SCLK signals are suggested for design considerations to prevent the occurrence of double
pulsing.
14.
Time required for valid output status data to be available on SO pin.
15.
Time required for output states data to be terminated at SO pin.
16.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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