參數(shù)資料
型號： K4T1G044QM
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1Gb M-die DDR2 SDRAM Specification
中文描述： 1Gb的的M -模DDR2 SDRAM的規(guī)格
文件頁數(shù)： 3/28頁
文件大?。?/td> 612K
代理商： K4T1G044QM
Page 3 of 28
Rev. 1.1 Aug. 2005
DDR2 SDRAM
1G A-die DDR2 SDRAM
Key Features
Speed
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
CAS Latency
5
4
3
tCK
tRCD(min)
15
15
15
ns
tRP(min)
15
15
15
ns
tRC(min)
54
55
55
ns
Ordering Information
Note 1 : Speed bin is in order of CL-tRCD-tRP.
Note 2 : x4/x8 Package - including 8 dummy balls.
Organization
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Package
256Mx4
K4T1G044QA-ZCE6
K4T1G044QA-ZCD5
K4T1G044QA-ZCCC
68 FBGA
128Mx8
K4T1G084QA-ZCE6
K4T1G084QA-ZCD5
K4T1G084QA-ZCCC
68 FBGA
64Mx16
K4T1G164QA-ZCE6
K4T1G164QA-ZCD5
K4T1G164QA-ZCCC
84 FBGA
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/
pin, 333MHz f
CK
for 667Mb/sec/pin
8 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
Special Function Support
-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable
Average Refresh Period 7.8us at lower than T
CASE
85
°
C,
3.9us at 85
°
C < T
CASE
< 95
°
C
Package: 68ball FBGA - 256Mx4/128Mx8 , 84ball FBGA -
64Mx16
All of Lead-free products are compliant for RoHS
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8
banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x4) device receive 14/
11/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 68ball FBGAs(x4/x8) and in
84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
相關(guān)PDF資料
PDF描述
K4T1G044QM-ZCD5 1Gb M-die DDR2 SDRAM Specification
K4T1G084QM-ZCD5 1Gb M-die DDR2 SDRAM Specification
K4T1G164QM-ZCD5 1Gb M-die DDR2 SDRAM Specification
K4T51043QC-ZLCC DIN Audio Connector; No. of Contacts:8; Contact Termination:Solder; Gender:Male RoHS Compliant: Yes
K4T51043QC-ZCLCC 512Mb C-die DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4T1G044QM-ZCCC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb M-die DDR2 SDRAM Specification
K4T1G044QM-ZCD5 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb M-die DDR2 SDRAM Specification
K4T1G044QQ 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb Q-die DDR2 SDRAM Specification
K4T1G044QQ-HC(L)E6 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb Q-die DDR2 SDRAM Specification
K4T1G044QQ-HC(L)E7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb Q-die DDR2 SDRAM Specification
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*