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參數(shù)資料
| 型號(hào)： | K4S281633D-RL |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | IC REG ULDO DUAL 2.8/1.5V 6-MLF |
| 中文描述： | 8M × 16位SDRAM的54CSP |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 71K |
| 代理商： | K4S281633D-RL |
K4S281633D-RL(N)
Rev. 0.6 Nov. 2001
CMOS SDRAM
Preliminary
3.0V & 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
.
DQM for masking.
Auto refresh.
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25
°
C ~ 70
°
C).
Extended Temperature Operation (-25
°
C ~ 85
°
C).
FEATURES
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
′
s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
GENERAL DESCRIPTION
2M x 16Bit x 4 Banks SDRAM in 54CSP
Bank Select
Data Input Register
2M x 16
2M x 16
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
* Samsung Electronics reserves the right to change products or specification without notice.
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
2M x 16
Timing Register
UDQM
FUNCTIONAL BLOCK DIAGRAM
Part No.
Max Freq.
133MHz(CL=3)
100MHz(CL=2)
Interface Package
K4S281633D-RL/N75
LVTTL
54 CSP
K4S281633D-RL/N1H
K4S281633D-RL/N1L 100MHz(CL=3)
*1
-RN ; Low Power, Operating Temperature : -25’ C~85’ C.
-RL ; Low Power, Operating Temperature : -25’ C~70’ C.
100MHz(CL=2)
1. In case of 40MHz Frequency, CL1 can be supported.
Note :
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| K4S281633D-N1H | 8Mx16 SDRAM 54CSP |
| K4S281633D-N1L | 8Mx16 SDRAM 54CSP |
| K4S281633D-N75 | 8Mx16 SDRAM 54CSP |
| K4S510432B-TC | 512Mb B-die SDRAM Specification |
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4S281633DRN75 | 制造商:Samsung Semiconductor 功能描述: |
| K4S283233F | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
| K4S283233F-C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
| K4S283233F-F1H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
| K4S283233F-F1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
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