參數(shù)資料
型號(hào)： K4S281632E-TL60
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128Mb E-die SDRAM Specification
中文描述： 128Mb的電子芯片內(nèi)存規(guī)格
文件頁(yè)數(shù)： 6/14頁(yè)
文件大?。?/td> 145K
代理商： K4S281632E-TL60
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.4 February. 2004
V
DD
N.C
V
DDQ
N.C
DQ0
V
SSQ
N.C
N.C
V
DDQ
N.C
DQ1
V
SSQ
N.C
V
DD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
PIN CONFIGURATION
(Top view)
V
SS
N.C
V
SSQ
N.C
DQ3
V
DDQ
N.C
N.C
V
SSQ
N.C
DQ2
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
,
Column address : (x4 : CA
0
~ CA
9
,CA
11
),
(x8 : CA
0
~ CA
9
),
(x16 : CA
0
~ CA
8
)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ
0
~
3
), (x8 : DQ
0
~
7
), (x16 : DQ
0
~
15
)
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
CS
Chip select
CKE
Clock enable
A
0
~ A
11
Address
BA
0
~ BA
1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
Data input/output mask
DQ
0
~
N
Data input/output
V
DD
/V
SS
Power supply/ground
V
DDQ
/V
SSQ
Data output power/ground
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
V
DD
DQ0
V
DDQ
N.C
DQ1
V
SSQ
N.C
DQ2
V
DDQ
N.C
DQ3
V
SSQ
N.C
V
DD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ7
V
SSQ
N.C
DQ6
V
DDQ
N.C
DQ5
V
SSQ
N.C
DQ4
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
x16
x8
x4
x16
x8
x4
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
相關(guān)PDF資料
PDF描述
K4S281632E-TL75 128Mb E-die SDRAM Specification
K4S281632F-TL60 128Mb F-die SDRAM Specification
K4S281632F-TL75 128Mb F-die SDRAM Specification
K4S281632F-UC60 CAP 0.1UF 100V 10% X7R SMD-1206 TR-7-PL 3K/REEL
K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4S281632ETL75 制造商:Samsung Semiconductor 功能描述:
K4S281632E-TL75 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb E-die SDRAM Specification
K4S281632F-TC60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb F-die SDRAM Specification
K4S281632F-TC75 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb F-die SDRAM Specification
K4S281632F-TCL60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb F-die SDRAM Specification
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*