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參數(shù)資料
| 型號(hào)： | K4S280432F-TL75 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TV 11C 11#12 PIN RECP |
| 中文描述： | 128Mb的的F - SDRAM內(nèi)存芯片規(guī)格 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | K4S280432F-TL75 |
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SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May 2004
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Unit
V
V
ns
V
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
Parameter
Symbol
Version
Unit
Note
60 (x16 only)
12
18
18
42
75
15
20
20
45
Row active to row active delay
RAS to CAS delay
Row precharge time
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
1
1
1
1
Row active time
100
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
60
65
1
2
2,5
5
2
2
3
2 CLK + tRP
1
1
1
2
Number of valid output data
CAS latency=3
CAS latency=2
ea
4
-
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
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