參數(shù)資料
型號(hào)： JZ48F4L0QBZ
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無(wú)線的StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 57/106頁(yè)
文件大?。?/td> 1272K
代理商： JZ48F4L0QBZ
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
57
10.3.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock
edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
10.3.8
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries. When BW is
set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may occur
when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s
start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word
boundary, the worst case output delay is one clock cycle less than the first access Latency Count.
This delay can take place only once, and doesn’t occur if the burst sequence does not cross a
device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the
flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 14, “Burst Sequence Word Ordering” on page 56
). When a burst cycle begins, the device
outputs synchronous burst data until it reaches the end of the “burstable” address space.
…
14
15
…
1
1
…
…
…
…
14-15-16-17-18…28-29
15-16-17-18-19…29-30
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Table 14.
Burst Sequence Word Ordering (Sheet 2 of 2)
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