參數(shù)資料
型號(hào)： JZ48F4L0BTY
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無線的StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 54/106頁(yè)
文件大?。?/td> 1272K
代理商： JZ48F4L0BTY
Intel StrataFlash Wireless Memory (L18)
April 2005
54
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V
OH
or V
OL
) of WAIT.
When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read status, read ID, or
read query the WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works correctly only
on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See
Figure
12, “Asynchronous Single-Word Read with ADV# Latch” on page 34
, and
Figure 13,
“Asynchronous Page-Mode Read Timing” on page 34
.
Figure 25.
Example Latency Count Setting
CLK
CE#
ADV#
A[MAX:0]
D[15:0]
t
Data
Code 3
Address
Data
0
1
2
3
4
R103
High-Z
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JZ48F4L0BTZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QBY 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QBZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QTY 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QTZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
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