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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
95
Table 23.
System Interface Information
C.4
Device Geometry Definition
Table 24.
Device Geometry Definition
Offset
Length
Description
Add.
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
Hex
Code
--51
--52
--59
--01
--00
--0A
--01
--00
--00
--00
--00
Value
"Q"
"R"
"Y"
10h
3
Query-unique ASCII string “QRY“
13h
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
15h
2
17h
2
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
19h
2
Offset
Length
Description
Add.
1B:
Hex
Code
--17
Value
1.7V
1Bh
1
1Ch
1
1C:
--20
2.0V
1Dh
1
1D:
--85
8.5V
1Eh
1
1E:
--95
9.5V
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
“n” such that typical single word program time-out = 2
n
μ-sec
“n” such that typical max. buffer write time-out = 2
n
μ-sec
“n” such that typical block erase time-out = 2
n
m-sec
“n” such that typical full chip erase time-out = 2
n
m-sec
“n” such that maximum word program time-out = 2
n
times typical
“n” such that maximum buffer write time-out = 2
n
times typical
“n” such that maximum block erase time-out = 2
n
times typical
“n” such that maximum chip erase time-out = 2
n
times typical
1F:
20:
21:
22:
23:
24:
25:
26:
--08
--09
--0A
--00
--01
--01
--02
--00
256μs
512μs
1s
NA
512μs
1024μs
4s
NA
V
PP
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
V
PP
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
V
CC
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
V
CC
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts