參數(shù)資料
型號(hào)： ISPPAC-CLK5620V-01TN100C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： Spot Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:530nm
中文描述： 5600 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝： LEAD FREE, TQFP-100
文件頁數(shù)： 20/47頁
文件大小： 871K
代理商： ISPPAC-CLK5620V-01TN100C
Lattice Semiconductor
ispClock5600 Family Data Sheet
20
Figure 14. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
REF
value, and the associated REFVTT or FBKVTT
terminal should be tied to a V
TT
termination supply. The positive input’s terminating resistor should be engaged and
set to 50
. Figure 15 shows an appropriate con
fi
guration. Refer to the “Recommended Operating Conditions -
Supported Logic Standards” table in this data sheet for suitable values of V
REF
and V
TT.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing
fl
uctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator speci
fi
cally designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration
R
T
OPEN
REFA-
REFA+
REFVTT
Single-ended
Receiver
No Connect
No Connect
Signal In
ispClock5600
50
CLOSED
REFA-
REFA+
REFVTT
VTT
Differential
Receiver
VREF IN
Signal In
ispClock5600
OPEN
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01TN100I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5620V-01TN100I Backlight LED; Color:Infrared; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5610V-01TN48C LED Ring Light; LED Color:Infrared; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:350mA; Supply Voltage:24VDC; Wavelength:880nm
ISPPAC-CLK5620V-01TN48C LED Area Light; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:630nm
ISPPAC-CLK5610V-01TN48I Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC-CLK5620V-01TN100I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5620V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5620V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-POWR1014 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR1014_08 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
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