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參數(shù)資料
| 型號： | ispLSI5512VA-125LB272 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| 中文描述： | 在系統(tǒng)可編程3.3超寬⑩高密度可編程邏輯器件 |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 331K |
| 代理商： | ISPLSI5512VA-125LB272 |
Specifications
ispLSI 5512VA
17
TMS
Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
TCK
Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
TDI
Input - This pin is the JTAG Test Data In pin used to load data.
TDO
Output - This pin is the JTAG Test Data Out pin used to shift data out.
TOE / I/O0
Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's
design. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1
Input - These two pins are the Global Output Enable input pins.
GSET/GRST
Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be
configured as preset, reset or no effect on each register. The global polarity (active high or low input)
for this pin is also selectable.
I/O
Input/Output
–
These are the general purpose I/O used by the logic array.
GND
Ground
NC
1
No connect.
VCC
Vcc
CLK0, CLK1
Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
CLK2 / I/O,
CLK3 / I/O
Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O
pin based upon customer's design. Both clocks are muxed before being used as the clock input
to all registers in the device.
VCCIO
Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must
be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current
from this supply.
Signal Descriptions
Signal Name
Description
1. NC pins are not to be connected to any active signals, VCC or GND.
相關PDF資料 |
PDF描述 |
|---|---|
| ispLSI5512VA-125LB388 | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| ispLSI5512VA-125LQ208 | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| ISPLSI5512VA-70LB272 | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| ISPLSI5512VA-70LB388 | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| ISPLSI5512VA-100LQ208 | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI5512VA-70LB272 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LB388 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LB388I | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LQ208 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-770LB272 | 制造商:Lattice Semiconductor Corporation 功能描述: |
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