參數(shù)資料
型號： ISPLSI5256VA-100LQ208
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： In-System Programmable 3.3V SuperWIDE⑩ High Density PLD
中文描述： EE PLD, 10 ns, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 14/25頁
文件大小： 311K
代理商： ISPLSI5256VA-100LQ208
Specifications
ispLSI 5256VA
14
Internal Timing Parameters
1
Over Recommended Operating Conditions
I/O Buffer
t
idcom
t
idreg
t
odcom
t
odreg
t
odz
t
slf
t
sls
t
slfd
t
slsd
GLB/Macrocell Delay Register
t
mbp
31
t
mlat
32
t
mco
33
t
msu
34
t
mh
35
t
msuce
36
t
mhce
37
t
mrst
38
t
ftog
39
AND Array
t
andhs
40
t
andlp
41
PTSA
t
5ptcom
42
t
5ptreg
43
t
5ptxcom
44
t
5pxtreg
45
t
ptsacom
46
t
ptsareg
47
PTSA Controls
t
pck
48
t
pcken
49
t
scken
50
t
sck
51
t
ptsacken
52
t
srst
53
t
prst
54
t
poe
55
t
gpoe
56
22
23
24
25
26
27
28
29
30
Input Pad and Buffer, Combinatorial Input
Input Pad and Buffer, Registered Input
Output Pad and Buffer, Combinatorial Output
Output Pad and Buffer, Registered Output
Output Buffer Enable/Disable
Slew Rate Adder, Fast Slew
Slew Rate Adder, Slow Slew
Programmable Delay Adder, Fast Slew
Programmable Delay Adder, Slow Slew
–
–
–
–
–
–
–
–
–
0.7
4.7
1.3
1.8
1.3
0
7.5
0.5
8
–
–
–
–
–
–
–
–
–
0.9
6.6
1.7
2.8
1.7
0
10
0.7
10.7
–
–
–
–
–
–
–
–
–
1.4
9.7
2.6
4.6
2.6
0
15
1
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
Macrocell Register/Latch Bypass
Macrocell Latch Delay
Macrocell Register/Latch Clock to Output
Macrocell Register/Latch Setup Time
Macrocell Register/Latch Hold Time
Macrocell Register/Latch CLKEN Setup Time
Macrocell Register/Latch CLKEN Hold Time
Macrocell Register/Latch Set/Reset Time
Toggle Flip-Flop Feedback
–
–
–
1
0
1
1
–
–
–
–
1
1
–
–
–
0
–
–
–
0
2
1
–
–
–
–
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.4
1
–
–
–
–
1.4
1.3
1.1
3.9
1.4
1.4
–
–
1.7
5.3
2
2
–
–
2.5
1
1
–
–
AND Array, High Speed Mode
AND Array, Low Power Mode
–
–
3
5
–
–
4
–
–
6
ns
ns
6.6
10
5 Product Term Bypass, Combinatorial
5 Product Term Bypass, Registered
5 Product Term XOR, Combinatorial
5 Product Term XOR, Registered
Product Term Sharing Array, Combinatorial
Product Term Sharing Array, Registered
–
–
–
–
–
–
1
1
–
–
–
–
–
–
1.4
1.7
3.6
2.2
4.1
2.7
–
–
–
–
–
–
2
ns
ns
ns
ns
ns
ns
2.3
5
3.3
6
4.3
2.5
1.5
3
2.0
Product Term Clock Delay
Product Term CLKEN Delay
Shared Product Term CLKEN Delay
Shared Product Term Clock Delay
Product Term Sharing Array CLKEN Delay
Shared Product Term Set/Reset Delay
Product Term Set/Reset Delay
Product Term Output Enable/Disable
Global PT Output Enable/Disable
–
–
–
–
–
–
–
–
–
0.5
1
1
0.5
2.0
2.5
1.5
2.5
11.5
–
–
–
–
–
–
–
–
–
0.7
1.4
1.4
0.7
2.4
3.4
2
3.4
15.4
–
–
–
–
–
–
–
–
–
1
2
2
1
4
5
3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
-125
-100
-70
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
PARAM
#
2
DESCRIPTION
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Timing Rev. 4.0
相關(guān)PDF資料
PDF描述
ISPLSI5256VA-70LQ208 In-System Programmable 3.3V SuperWIDE⑩ High Density PLD
ISPLSI5256VA-125LB208 In-System Programmable 3.3V SuperWIDE⑩ High Density PLD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI5256VA-125LB208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA-125LB272 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA125LQ208 制造商:Lattice 功能描述:_
ISPLSI5256VA-125LQ208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA-70LB208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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