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參數(shù)資料
| 型號(hào)： | ISPLSI3256E-100LB320 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 10 ns, PBGA320 |
| 封裝： | BGA-320 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 159K |
| 代理商： | ISPLSI3256E-100LB320 |
Specifications
ispLSI 3256E
3
Description (continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 256 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The 256 I/O Cells are grouped into 16 sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.
Four Twin GLBs, 32 I/O Cells and two ORPs are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the ORP. The ispLSI 3256E device
contains eight of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Clocks in the ispLSI 3256E device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3256E is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The ispLSI 3256E supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3256E
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI3256E-70LB320 | In-System Programmable High Density PLD |
| ISPLSI3256E-70LQ | In-System Programmable High Density PLD |
| ISPLSI3256E-100LQ | In-System Programmable High Density PLD |
| ISPLSI3448 | In-System Programmable High Density PLD |
| ISPLSI5128VE | In-System Programmable 3.3V SuperWIDE High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI3256E-70LB320 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI-3256E-70LQ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI3256E-70LQ | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE HIGH DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI3256E-70LQA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI3320-100LQ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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