參數(shù)資料
型號(hào): ISPLSI2128V-60LT176
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V High Density Programmable Logic
中文描述: EE PLD, 20 ns, PQFP176
封裝: TQFP-176
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 151K
代理商: ISPLSI2128V-60LT176
Specifications
ispLSI 2128V
7
USEispLS 2128VEFORNEWDESGNS
ispLSI 2128V Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33, 34,
35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25, 26, 27
#43, 44
#36
Reset
Ded. In
#21
#29, 30,
31, 32
#38,
39
GOE 0
#42
#40, 41
0491/2032
Comb 4 PT Bypass #23
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
5.9 ns
=
(0.4 + 1.2 + 9.5) + (0.2) - (0.4 + 1.2 + 3.8)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.4 + 1.2 + 5.6) + (5.4) - (0.4 + 1.2 + 9.5)
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
=
=
=
=
1.5 ns
=
=
=
t
co
12.4 ns =
Note: Calculations are based upon timing specifications for the ispLSI 2128V-80L.
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.4 + 1.2 + 5.6) + (1.6) + (1.4 + 2.2)
Table 2-0042/2128V
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