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參數(shù)資料
| 型號： | ISPLSI2128V-60LQ160I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V High Density Programmable Logic |
| 中文描述： | 3.3高密度可編程邏輯 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 151K |
| 代理商： | ISPLSI2128V-60LQ160I |
ispLSI
2128V
3.3V High Density Programmable Logic
2128v_14
1
USEispLS 2128VEFORNEWDESGNS
Features
HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
3.3V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 128 I/O Pin Version is Fuse Map Compatible
with 5V ispLSI 2128
HIGH PERFORMANCE E
CMOS
TECHNOLOGY
—
f
max
= 80 MHz Maximum Operating Frequency
—
t
pd
= 10 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Functional Block Diagram*
Description
The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 2128V features in-
system programmability through the Boundary Scan
Test Access Port (TAP). The ispLSI 2128V offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Global Routing Pool (GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C
C
C
Logic
Array
GLB
Q
Q
Q
Q
0139A/2128V
C7
C6
C5
C4
C3
C2
C1
C0
B4
B5
B6
B7
B0
B1
B2
B3
A0
A1
A2
A3
A4
A5
A6
A7
*128 I/O Version Shown
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
相關PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2128V-60LT100I | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT176 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT176I | 3.3V High Density Programmable Logic |
| ISPLSI2128V-80LJ84 | 3.3V High Density Programmable Logic |
| ISPLSI2128V-80LJ84I | 3.3V High Density Programmable Logic |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI2128V60LT100 | 制造商:LATTICE 功能描述:* |
| ISPLSI2128V-60LT100 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT176 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2128V-60LT176I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
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